Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T21
1	0	Covered	T2,T16,T3
1	1	Covered	T21,T2,T16

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	392197674	4089	0	0
g_div2.Div2Whole_A	392197674	4928	0	0
g_div4.Div4Stepped_A	195580082	4003	0	0
g_div4.Div4Whole_A	195580082	4628	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392197674	4089	0	0
T2	481697	63	0	0
T3	374339	79	0	0
T16	1401	0	0	0
T17	2252	0	0	0
T18	5756	0	0	0
T19	3788	4	0	0
T20	6312	0	0	0
T21	4802	2	0	0
T26	1820	5	0	0
T27	2297	0	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	0	2	0	0
T103	0	4	0	0
T104	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392197674	4928	0	0
T2	481697	74	0	0
T3	374339	90	0	0
T16	1401	1	0	0
T17	2252	0	0	0
T18	5756	0	0	0
T19	3788	7	0	0
T20	6312	0	0	0
T21	4802	3	0	0
T26	1820	5	0	0
T27	2297	0	0	0
T100	0	6	0	0
T101	0	5	0	0
T102	0	3	0	0
T104	0	9	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195580082	4003	0	0
T2	240848	63	0	0
T3	186812	77	0	0
T16	682	0	0	0
T17	1059	0	0	0
T18	2838	0	0	0
T19	1944	4	0	0
T20	3102	0	0	0
T21	2517	2	0	0
T26	1514	5	0	0
T27	1095	0	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	4	0	0
T104	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195580082	4628	0	0
T2	240848	74	0	0
T3	186812	81	0	0
T16	682	1	0	0
T17	1059	0	0	0
T18	2838	0	0	0
T19	1944	7	0	0
T20	3102	0	0	0
T21	2517	3	0	0
T26	1514	5	0	0
T27	1095	0	0	0
T100	0	5	0	0
T101	0	5	0	0
T102	0	3	0	0
T104	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T21
1	0	Covered	T2,T16,T3
1	1	Covered	T21,T2,T16

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	392197674	4089	0	0
g_div2.Div2Whole_A	392197674	4928	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392197674	4089	0	0
T2	481697	63	0	0
T3	374339	79	0	0
T16	1401	0	0	0
T17	2252	0	0	0
T18	5756	0	0	0
T19	3788	4	0	0
T20	6312	0	0	0
T21	4802	2	0	0
T26	1820	5	0	0
T27	2297	0	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	0	2	0	0
T103	0	4	0	0
T104	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392197674	4928	0	0
T2	481697	74	0	0
T3	374339	90	0	0
T16	1401	1	0	0
T17	2252	0	0	0
T18	5756	0	0	0
T19	3788	7	0	0
T20	6312	0	0	0
T21	4802	3	0	0
T26	1820	5	0	0
T27	2297	0	0	0
T100	0	6	0	0
T101	0	5	0	0
T102	0	3	0	0
T104	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T21
1	0	Covered	T2,T16,T3
1	1	Covered	T21,T2,T16

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	195580082	4003	0	0
g_div4.Div4Whole_A	195580082	4628	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195580082	4003	0	0
T2	240848	63	0	0
T3	186812	77	0	0
T16	682	0	0	0
T17	1059	0	0	0
T18	2838	0	0	0
T19	1944	4	0	0
T20	3102	0	0	0
T21	2517	2	0	0
T26	1514	5	0	0
T27	1095	0	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	4	0	0
T104	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195580082	4628	0	0
T2	240848	74	0	0
T3	186812	81	0	0
T16	682	1	0	0
T17	1059	0	0	0
T18	2838	0	0	0
T19	1944	7	0	0
T20	3102	0	0	0
T21	2517	3	0	0
T26	1514	5	0	0
T27	1095	0	0	0
T100	0	5	0	0
T101	0	5	0	0
T102	0	3	0	0
T104	0	9	0	0