Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	46995	0	0
CgEnOn_A	2147483647	37448	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46995	0	0
T1	823963	3	0	0
T2	3182068	334	0	0
T3	3256728	365	0	0
T4	383183	18	0	0
T5	21428	47	0	0
T6	62478	7	0	0
T16	8964	3	0	0
T17	14345	18	0	0
T18	36869	12	0	0
T19	15780	0	0	0
T20	0	4	0	0
T21	10978	3	0	0
T24	0	5	0	0
T25	0	10	0	0
T27	0	1	0	0
T31	117715	0	0	0
T42	0	10	0	0
T43	0	5	0	0
T44	7377	24	0	0
T45	9358	20	0	0
T101	15238	0	0	0
T129	0	15	0	0
T130	0	15	0	0
T131	0	10	0	0
T136	15084	0	0	0
T137	18806	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37448	0	0
T1	823963	0	0	0
T2	3182068	184	0	0
T3	3256728	175	0	0
T4	383183	0	0	0
T5	21428	35	0	0
T6	62478	0	0	0
T10	0	91	0	0
T16	8964	0	0	0
T17	14345	10	0	0
T18	36869	0	0	0
T19	24375	0	0	0
T24	0	4	0	0
T25	0	9	0	0
T27	0	2	0	0
T31	117715	0	0	0
T32	0	2	0	0
T42	0	8	0	0
T43	0	4	0	0
T44	7377	28	0	0
T45	9358	20	0	0
T101	15238	0	0	0
T105	0	2	0	0
T129	0	15	0	0
T130	0	15	0	0
T131	0	10	0	0
T132	0	1	0	0
T133	0	4	0	0
T134	0	1	0	0
T136	15084	0	0	0
T137	18806	0	0	0
T139	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	195579677	124	0	0
CgEnOn_A	195579677	124	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195579677	124	0	0
T1	38285	0	0	0
T4	12711	0	0	0
T5	963	5	0	0
T6	2896	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T31	8793	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	851	4	0	0
T45	1034	4	0	0
T101	1778	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	2	0	0
T136	1693	0	0	0
T137	2378	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195579677	124	0	0
T1	38285	0	0	0
T4	12711	0	0	0
T5	963	5	0	0
T6	2896	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T31	8793	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	851	4	0	0
T45	1034	4	0	0
T101	1778	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	2	0	0
T136	1693	0	0	0
T137	2378	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97789256	124	0	0
CgEnOn_A	97789256	124	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97789256	124	0	0
T1	19143	0	0	0
T4	6356	0	0	0
T5	482	5	0	0
T6	1448	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T31	4396	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	425	4	0	0
T45	517	4	0	0
T101	889	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	2	0	0
T136	846	0	0	0
T137	1187	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97789256	124	0	0
T1	19143	0	0	0
T4	6356	0	0	0
T5	482	5	0	0
T6	1448	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T31	4396	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	425	4	0	0
T45	517	4	0	0
T101	889	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	2	0	0
T136	846	0	0	0
T137	1187	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	392197232	124	0	0
CgEnOn_A	392197232	114	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392197232	124	0	0
T1	76664	0	0	0
T4	37981	0	0	0
T5	2047	5	0	0
T6	5816	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T31	31048	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	1753	4	0	0
T45	2175	4	0	0
T101	3501	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	2	0	0
T136	3519	0	0	0
T137	4173	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392197232	114	0	0
T1	76664	0	0	0
T4	37981	0	0	0
T5	2047	5	0	0
T6	5816	0	0	0
T25	0	1	0	0
T31	31048	0	0	0
T44	1753	4	0	0
T45	2175	4	0	0
T101	3501	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	2	0	0
T132	0	1	0	0
T133	0	4	0	0
T134	0	1	0	0
T136	3519	0	0	0
T137	4173	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	418723262	118	0	0
CgEnOn_A	418723262	117	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	118	0	0
T1	79860	0	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	0	0	0
T24	0	1	0	0
T31	32343	0	0	0
T44	1749	4	0	0
T45	2299	6	0	0
T101	3646	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	3	0	0
T135	0	6	0	0
T136	3667	0	0	0
T137	4347	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	117	0	0
T1	79860	0	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	0	0	0
T31	32343	0	0	0
T44	1749	4	0	0
T45	2299	6	0	0
T101	3646	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	3	0	0
T135	0	6	0	0
T136	3667	0	0	0
T137	4347	0	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97789256	124	0	0
CgEnOn_A	97789256	124	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97789256	124	0	0
T1	19143	0	0	0
T4	6356	0	0	0
T5	482	5	0	0
T6	1448	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T31	4396	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	425	4	0	0
T45	517	4	0	0
T101	889	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	2	0	0
T136	846	0	0	0
T137	1187	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97789256	124	0	0
T1	19143	0	0	0
T4	6356	0	0	0
T5	482	5	0	0
T6	1448	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T31	4396	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	425	4	0	0
T45	517	4	0	0
T101	889	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	2	0	0
T136	846	0	0	0
T137	1187	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	418723262	118	0	0
CgEnOn_A	418723262	117	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	118	0	0
T1	79860	0	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	0	0	0
T24	0	1	0	0
T31	32343	0	0	0
T44	1749	4	0	0
T45	2299	6	0	0
T101	3646	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	3	0	0
T135	0	6	0	0
T136	3667	0	0	0
T137	4347	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	117	0	0
T1	79860	0	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	0	0	0
T31	32343	0	0	0
T44	1749	4	0	0
T45	2299	6	0	0
T101	3646	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	3	0	0
T135	0	6	0	0
T136	3667	0	0	0
T137	4347	0	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97789256	124	0	0
CgEnOn_A	97789256	124	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97789256	124	0	0
T1	19143	0	0	0
T4	6356	0	0	0
T5	482	5	0	0
T6	1448	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T31	4396	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	425	4	0	0
T45	517	4	0	0
T101	889	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	2	0	0
T136	846	0	0	0
T137	1187	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97789256	124	0	0
T1	19143	0	0	0
T4	6356	0	0	0
T5	482	5	0	0
T6	1448	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T31	4396	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	425	4	0	0
T45	517	4	0	0
T101	889	0	0	0
T129	0	3	0	0
T130	0	3	0	0
T131	0	2	0	0
T136	846	0	0	0
T137	1187	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T44,T45
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	195579677	7581	0	0
CgEnOn_A	195579677	5203	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195579677	7581	0	0
T1	38285	1	0	0
T2	240848	97	0	0
T3	186812	97	0	0
T4	12711	6	0	0
T5	963	6	0	0
T6	2896	1	0	0
T16	682	1	0	0
T17	1059	6	0	0
T18	2838	1	0	0
T21	2517	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195579677	5203	0	0
T1	38285	0	0	0
T2	240848	91	0	0
T3	186812	86	0	0
T4	12711	0	0	0
T5	963	5	0	0
T6	2896	0	0	0
T10	0	48	0	0
T16	682	0	0	0
T17	1059	5	0	0
T18	2838	0	0	0
T19	1943	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	4	0	0
T105	0	1	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T44,T45
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97789256	7213	0	0
CgEnOn_A	97789256	4836	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97789256	7213	0	0
T1	19143	1	0	0
T2	120423	99	0	0
T3	934043	100	0	0
T4	6356	6	0	0
T5	482	6	0	0
T6	1448	1	0	0
T16	341	1	0	0
T17	529	6	0	0
T18	1419	1	0	0
T21	1258	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97789256	4836	0	0
T1	19143	0	0	0
T2	120423	93	0	0
T3	934043	89	0	0
T4	6356	0	0	0
T5	482	5	0	0
T6	1448	0	0	0
T10	0	43	0	0
T16	341	0	0	0
T17	529	5	0	0
T18	1419	0	0	0
T19	972	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	4	0	0
T105	0	1	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T44,T45
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	392197232	7829	0	0
CgEnOn_A	392197232	5442	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392197232	7829	0	0
T1	76664	1	0	0
T2	481697	95	0	0
T3	374339	103	0	0
T4	37981	6	0	0
T5	2047	6	0	0
T6	5816	1	0	0
T16	1401	1	0	0
T17	2251	6	0	0
T18	5755	1	0	0
T21	4802	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392197232	5442	0	0
T1	76664	0	0	0
T2	481697	89	0	0
T3	374339	92	0	0
T4	37981	0	0	0
T5	2047	5	0	0
T6	5816	0	0	0
T10	0	48	0	0
T16	1401	0	0	0
T17	2251	5	0	0
T18	5755	0	0	0
T19	3787	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	4	0	0
T105	0	1	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T44,T45
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	201059456	7612	0	0
CgEnOn_A	201059456	5222	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201059456	7612	0	0
T1	38333	1	0	0
T2	250364	105	0	0
T3	188918	101	0	0
T4	18991	6	0	0
T5	1054	2	0	0
T6	2908	1	0	0
T16	700	1	0	0
T17	1126	5	0	0
T18	2877	1	0	0
T21	2401	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201059456	5222	0	0
T1	38333	0	0	0
T2	250364	99	0	0
T3	188918	90	0	0
T4	18991	0	0	0
T5	1054	1	0	0
T6	2908	0	0	0
T10	0	50	0	0
T16	700	0	0	0
T17	1126	4	0	0
T18	2877	0	0	0
T19	1893	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	3	0	0
T105	0	1	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Covered	T6,T2,T3
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	418723262	4016	0	0
CgEnOn_A	418723262	4015	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	4016	0	0
T1	79860	0	0	0
T2	522184	43	0	0
T3	393154	65	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	4	0	0
T16	1460	0	0	0
T17	2345	0	0	0
T18	5995	9	0	0
T19	3945	0	0	0
T20	0	4	0	0
T27	0	1	0	0
T28	0	3	0	0
T32	0	30	0	0
T44	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	4015	0	0
T1	79860	0	0	0
T2	522184	43	0	0
T3	393154	65	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	4	0	0
T16	1460	0	0	0
T17	2345	0	0	0
T18	5995	9	0	0
T19	3945	0	0	0
T20	0	4	0	0
T27	0	1	0	0
T28	0	3	0	0
T32	0	30	0	0
T44	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Covered	T6,T2,T3
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	418723262	3957	0	0
CgEnOn_A	418723262	3956	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	3957	0	0
T1	79860	0	0	0
T2	522184	51	0	0
T3	393154	52	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	2	0	0
T16	1460	0	0	0
T17	2345	0	0	0
T18	5995	5	0	0
T19	3945	0	0	0
T20	0	4	0	0
T27	0	1	0	0
T28	0	4	0	0
T32	0	34	0	0
T44	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	3956	0	0
T1	79860	0	0	0
T2	522184	51	0	0
T3	393154	52	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	2	0	0
T16	1460	0	0	0
T17	2345	0	0	0
T18	5995	5	0	0
T19	3945	0	0	0
T20	0	4	0	0
T27	0	1	0	0
T28	0	4	0	0
T32	0	34	0	0
T44	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Covered	T6,T2,T3
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	418723262	4022	0	0
CgEnOn_A	418723262	4021	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	4022	0	0
T1	79860	0	0	0
T2	522184	48	0	0
T3	393154	65	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	4	0	0
T16	1460	0	0	0
T17	2345	0	0	0
T18	5995	7	0	0
T19	3945	0	0	0
T20	0	5	0	0
T27	0	1	0	0
T28	0	1	0	0
T32	0	25	0	0
T44	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	4021	0	0
T1	79860	0	0	0
T2	522184	48	0	0
T3	393154	65	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	4	0	0
T16	1460	0	0	0
T17	2345	0	0	0
T18	5995	7	0	0
T19	3945	0	0	0
T20	0	5	0	0
T27	0	1	0	0
T28	0	1	0	0
T32	0	25	0	0
T44	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T2
1	0	Covered	T6,T2,T3
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	418723262	3909	0	0
CgEnOn_A	418723262	3909	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	3909	0	0
T1	79860	0	0	0
T2	522184	52	0	0
T3	393154	55	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	4	0	0
T16	1460	0	0	0
T17	2345	0	0	0
T18	5995	8	0	0
T19	3945	0	0	0
T20	0	3	0	0
T27	0	1	0	0
T28	0	4	0	0
T32	0	31	0	0
T44	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418723262	3909	0	0
T1	79860	0	0	0
T2	522184	52	0	0
T3	393154	55	0	0
T4	39564	0	0	0
T5	2071	4	0	0
T6	6059	4	0	0
T16	1460	0	0	0
T17	2345	0	0	0
T18	5995	8	0	0
T19	3945	0	0	0
T20	0	3	0	0
T27	0	1	0	0
T28	0	4	0	0
T32	0	31	0	0
T44	0	4	0	0