Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T17
0	1	Covered	T2,T17,T3
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T3
1	0	Covered	T5,T44,T45
1	1	Covered	T5,T1,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	886627292	13880	0	0
GateOpen_A	886627292	13873	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886627292	13880	0	0
T1	172427	0	0	0
T2	1093332	221	0	0
T3	1684113	224	0	0
T4	76040	0	0	0
T5	4547	16	0	0
T6	13069	0	0	0
T10	0	141	0	0
T16	3126	0	0	0
T17	4967	16	0	0
T18	12891	0	0	0
T19	8598	0	0	0
T27	0	4	0	0
T32	0	4	0	0
T44	0	15	0	0
T105	0	4	0	0
T139	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886627292	13873	0	0
T1	172427	0	0	0
T2	1093332	221	0	0
T3	1684113	224	0	0
T4	76040	0	0	0
T5	4547	16	0	0
T6	13069	0	0	0
T10	0	141	0	0
T16	3126	0	0	0
T17	4967	16	0	0
T18	12891	0	0	0
T19	8598	0	0	0
T27	0	4	0	0
T32	0	4	0	0
T44	0	15	0	0
T105	0	4	0	0
T139	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T17
0	1	Covered	T2,T17,T3
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T3
1	0	Covered	T5,T44,T45
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	97789650	3374	0	0
GateOpen_A	97789650	3372	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97789650	3374	0	0
T1	19143	0	0	0
T2	120423	58	0	0
T3	934044	56	0	0
T4	6356	0	0	0
T5	482	5	0	0
T6	1448	0	0	0
T10	0	34	0	0
T16	342	0	0	0
T17	530	4	0	0
T18	1419	0	0	0
T19	972	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	4	0	0
T105	0	1	0	0
T139	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97789650	3372	0	0
T1	19143	0	0	0
T2	120423	58	0	0
T3	934044	56	0	0
T4	6356	0	0	0
T5	482	5	0	0
T6	1448	0	0	0
T10	0	34	0	0
T16	342	0	0	0
T17	530	4	0	0
T18	1419	0	0	0
T19	972	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	4	0	0
T105	0	1	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T17
0	1	Covered	T2,T17,T3
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T3
1	0	Covered	T5,T44,T45
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	195580082	3484	0	0
GateOpen_A	195580082	3482	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195580082	3484	0	0
T1	38286	0	0	0
T2	240848	53	0	0
T3	186812	53	0	0
T4	12712	0	0	0
T5	964	5	0	0
T6	2896	0	0	0
T10	0	36	0	0
T16	682	0	0	0
T17	1059	4	0	0
T18	2838	0	0	0
T19	1944	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	4	0	0
T105	0	1	0	0
T139	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195580082	3482	0	0
T1	38286	0	0	0
T2	240848	53	0	0
T3	186812	53	0	0
T4	12712	0	0	0
T5	964	5	0	0
T6	2896	0	0	0
T10	0	36	0	0
T16	682	0	0	0
T17	1059	4	0	0
T18	2838	0	0	0
T19	1944	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	4	0	0
T105	0	1	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T17
0	1	Covered	T2,T17,T3
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T3
1	0	Covered	T5,T44,T45
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	392197674	3527	0	0
GateOpen_A	392197674	3525	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392197674	3527	0	0
T1	76664	0	0	0
T2	481697	53	0	0
T3	374339	57	0	0
T4	37981	0	0	0
T5	2047	5	0	0
T6	5816	0	0	0
T10	0	37	0	0
T16	1401	0	0	0
T17	2252	4	0	0
T18	5756	0	0	0
T19	3788	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	4	0	0
T105	0	1	0	0
T139	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392197674	3525	0	0
T1	76664	0	0	0
T2	481697	53	0	0
T3	374339	57	0	0
T4	37981	0	0	0
T5	2047	5	0	0
T6	5816	0	0	0
T10	0	37	0	0
T16	1401	0	0	0
T17	2252	4	0	0
T18	5756	0	0	0
T19	3788	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	4	0	0
T105	0	1	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T17
0	1	Covered	T2,T17,T3
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T3
1	0	Covered	T5,T44,T45
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	201059886	3495	0	0
GateOpen_A	201059886	3494	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201059886	3495	0	0
T1	38334	0	0	0
T2	250364	57	0	0
T3	188918	58	0	0
T4	18991	0	0	0
T5	1054	1	0	0
T6	2909	0	0	0
T10	0	34	0	0
T16	701	0	0	0
T17	1126	4	0	0
T18	2878	0	0	0
T19	1894	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	3	0	0
T105	0	1	0	0
T139	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201059886	3494	0	0
T1	38334	0	0	0
T2	250364	57	0	0
T3	188918	58	0	0
T4	18991	0	0	0
T5	1054	1	0	0
T6	2909	0	0	0
T10	0	34	0	0
T16	701	0	0	0
T17	1126	4	0	0
T18	2878	0	0	0
T19	1894	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T44	0	3	0	0
T105	0	1	0	0
T139	0	1	0	0