Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	543783	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3004311

1

T6

70

T7

14

T8

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	874629	1			T6	78		T8	20		T30	458
values[0x0]	1228914	1			T6	39		T7	17		T8	21
values[0x1]	1444551	1			T6	28		T7	18		T8	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	304885	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3243209

1

T6

83

T7

17

T8

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12845	1			T6	1		T30	1		T31	17
valid_sources[0x01]	13581	1			T31	4		T32	17		T35	3
valid_sources[0x02]	13825	1			T6	2		T30	3		T31	4
valid_sources[0x03]	12911	1			T31	14		T32	7		T34	1
valid_sources[0x04]	12888	1			T30	2		T31	8		T32	17
valid_sources[0x05]	13472	1			T6	1		T30	1		T31	15
valid_sources[0x06]	13539	1			T8	1		T30	3		T31	5
valid_sources[0x07]	13841	1			T30	2		T31	7		T32	13
valid_sources[0x08]	14335	1			T6	4		T30	1		T31	12
valid_sources[0x09]	13859	1			T8	1		T31	7		T32	6
valid_sources[0x0a]	13537	1			T30	3		T31	7		T32	9
valid_sources[0x0b]	14258	1			T6	1		T30	1		T31	16
valid_sources[0x0c]	14750	1			T30	1		T31	14		T32	5
valid_sources[0x0d]	13730	1			T30	1		T31	10		T32	7
valid_sources[0x0e]	13190	1			T30	4		T31	14		T32	10
valid_sources[0x0f]	13558	1			T30	4		T31	10		T32	10
valid_sources[0x10]	14190	1			T8	1		T30	5		T31	5
valid_sources[0x11]	13690	1			T6	1		T31	9		T32	9
valid_sources[0x12]	14015	1			T31	7		T32	13		T33	10
valid_sources[0x13]	13051	1			T30	3		T31	9		T32	11
valid_sources[0x14]	14745	1			T6	1		T30	2		T31	12
valid_sources[0x15]	13381	1			T6	3		T30	1		T31	7
valid_sources[0x16]	13360	1			T31	9		T32	8		T34	6
valid_sources[0x17]	12081	1			T6	1		T8	1		T30	1
valid_sources[0x18]	13985	1			T30	2		T31	13		T32	2
valid_sources[0x19]	13033	1			T6	3		T30	1		T31	7
valid_sources[0x1a]	12602	1			T6	1		T8	1		T30	3
valid_sources[0x1b]	14491	1			T31	6		T32	8		T34	3
valid_sources[0x1c]	14494	1			T30	5		T31	4		T32	13
valid_sources[0x1d]	13287	1			T6	1		T30	2		T31	10
valid_sources[0x1e]	13076	1			T6	2		T30	1		T31	5
valid_sources[0x1f]	14521	1			T30	1		T31	6		T32	8
valid_sources[0x20]	13908	1			T31	4		T32	4		T49	3
valid_sources[0x21]	14546	1			T31	5		T32	9		T34	1
valid_sources[0x22]	13360	1			T6	4		T30	3		T31	19
valid_sources[0x23]	13974	1			T30	4		T31	9		T32	8
valid_sources[0x24]	13233	1			T6	1		T30	1		T31	6
valid_sources[0x25]	13362	1			T30	3		T31	5		T32	6
valid_sources[0x26]	13244	1			T6	1		T30	2		T31	8
valid_sources[0x27]	13354	1			T8	1		T30	1		T31	9
valid_sources[0x28]	13550	1			T8	1		T31	8		T32	6
valid_sources[0x29]	14094	1			T30	1		T31	11		T32	9
valid_sources[0x2a]	14910	1			T6	1		T8	2		T30	3
valid_sources[0x2b]	14153	1			T6	1		T30	11		T31	9
valid_sources[0x2c]	14105	1			T6	1		T30	5		T31	6
valid_sources[0x2d]	14320	1			T8	1		T30	1		T31	4
valid_sources[0x2e]	13245	1			T6	2		T8	1		T30	1
valid_sources[0x2f]	12848	1			T6	1		T8	1		T30	2
valid_sources[0x30]	14133	1			T31	11		T32	1		T34	6
valid_sources[0x31]	12554	1			T30	3		T31	15		T32	6
valid_sources[0x32]	15103	1			T6	1		T30	2		T31	6
valid_sources[0x33]	13142	1			T6	1		T31	16		T32	9
valid_sources[0x34]	14233	1			T6	2		T30	4		T31	6
valid_sources[0x35]	14446	1			T6	1		T30	2		T31	9
valid_sources[0x36]	12990	1			T8	1		T30	1		T31	3
valid_sources[0x37]	14106	1			T8	2		T30	1		T31	6
valid_sources[0x38]	14223	1			T30	2		T31	7		T32	12
valid_sources[0x39]	12927	1			T30	6		T31	7		T32	4
valid_sources[0x3a]	12845	1			T8	1		T31	15		T32	10
valid_sources[0x3b]	13663	1			T8	1		T31	13		T32	14
valid_sources[0x3c]	13398	1			T6	2		T30	2		T31	6
valid_sources[0x3d]	13962	1			T6	2		T30	3		T31	14
valid_sources[0x3e]	13294	1			T6	1		T8	1		T30	6
valid_sources[0x3f]	14368	1			T31	4		T32	8		T36	2
valid_sources[0x40]	13958	1			T30	1		T31	10		T32	8
valid_sources[0x41]	13706	1			T6	2		T8	1		T30	1
valid_sources[0x42]	12758	1			T31	12		T32	12		T48	1
valid_sources[0x43]	15693	1			T6	1		T31	7		T32	7
valid_sources[0x44]	13593	1			T6	1		T30	2		T31	11
valid_sources[0x45]	14538	1			T8	1		T30	3		T31	5
valid_sources[0x46]	13355	1			T30	4		T31	5		T32	10
valid_sources[0x47]	12373	1			T30	1		T31	7		T32	5
valid_sources[0x48]	12475	1			T30	1		T31	5		T32	10
valid_sources[0x49]	14050	1			T31	12		T32	5		T34	2
valid_sources[0x4a]	14384	1			T30	4		T31	11		T32	9
valid_sources[0x4b]	12819	1			T6	1		T30	1		T31	7
valid_sources[0x4c]	13331	1			T6	1		T30	2		T31	9
valid_sources[0x4d]	13023	1			T6	1		T30	3		T31	9
valid_sources[0x4e]	15203	1			T31	8		T32	6		T34	3
valid_sources[0x4f]	14354	1			T30	2		T31	7		T32	6
valid_sources[0x50]	14708	1			T6	1		T30	2		T31	7
valid_sources[0x51]	14623	1			T30	2		T31	8		T32	10
valid_sources[0x52]	13000	1			T30	2		T31	7		T32	7
valid_sources[0x53]	13875	1			T6	1		T31	15		T32	10
valid_sources[0x54]	13722	1			T30	4		T31	11		T32	7
valid_sources[0x55]	14048	1			T30	1		T31	7		T32	14
valid_sources[0x56]	13846	1			T6	1		T30	3		T31	10
valid_sources[0x57]	13568	1			T30	2		T31	3		T32	7
valid_sources[0x58]	14482	1			T30	2		T31	9		T32	3
valid_sources[0x59]	13121	1			T8	1		T30	2		T31	11
valid_sources[0x5a]	14288	1			T8	3		T30	3		T31	8
valid_sources[0x5b]	14339	1			T30	3		T31	8		T32	8
valid_sources[0x5c]	13142	1			T30	1		T31	6		T32	6
valid_sources[0x5d]	14070	1			T6	3		T30	4		T31	6
valid_sources[0x5e]	12887	1			T6	1		T30	4		T31	5
valid_sources[0x5f]	13167	1			T6	4		T30	1		T31	9
valid_sources[0x60]	13747	1			T30	4		T31	7		T32	14
valid_sources[0x61]	13614	1			T30	6		T31	7		T32	18
valid_sources[0x62]	13777	1			T30	1		T31	5		T32	7
valid_sources[0x63]	13056	1			T6	2		T8	1		T30	3
valid_sources[0x64]	13822	1			T30	2		T31	3		T32	6
valid_sources[0x65]	14356	1			T30	1		T31	3		T32	3
valid_sources[0x66]	14306	1			T31	6		T32	11		T34	5
valid_sources[0x67]	12688	1			T6	1		T30	1		T31	5
valid_sources[0x68]	13735	1			T8	1		T31	9		T32	15
valid_sources[0x69]	12218	1			T6	2		T31	7		T32	10
valid_sources[0x6a]	13714	1			T30	3		T31	7		T32	10
valid_sources[0x6b]	13828	1			T31	12		T32	14		T34	2
valid_sources[0x6c]	13665	1			T6	1		T8	1		T31	12
valid_sources[0x6d]	13627	1			T6	2		T30	2		T31	6
valid_sources[0x6e]	14375	1			T31	9		T32	4		T34	7
valid_sources[0x6f]	13505	1			T6	1		T30	1		T31	6
valid_sources[0x70]	12795	1			T30	4		T31	10		T32	11
valid_sources[0x71]	13273	1			T6	1		T30	1		T31	6
valid_sources[0x72]	13453	1			T30	3		T31	7		T32	16
valid_sources[0x73]	13664	1			T8	1		T30	1		T31	8
valid_sources[0x74]	13394	1			T6	1		T30	1		T31	7
valid_sources[0x75]	13270	1			T6	2		T8	1		T30	3
valid_sources[0x76]	13952	1			T7	35		T30	2		T31	10
valid_sources[0x77]	13687	1			T30	2		T31	11		T32	6
valid_sources[0x78]	14633	1			T8	1		T30	3		T31	14
valid_sources[0x79]	14407	1			T6	1		T30	2		T31	10
valid_sources[0x7a]	14722	1			T8	1		T31	12		T32	11
valid_sources[0x7b]	13962	1			T6	1		T30	3		T31	10
valid_sources[0x7c]	14757	1			T30	2		T31	5		T32	8
valid_sources[0x7d]	14416	1			T30	1		T31	11		T32	7
valid_sources[0x7e]	14426	1			T6	3		T30	2		T31	17
valid_sources[0x7f]	14981	1			T30	2		T31	4		T32	9
valid_sources[0x80]	14158	1			T30	1		T31	6		T32	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

759468

1

T6

47

T8

9

T30

197

values[0x0]

all_enables

biggest_size

1142829

1

T6

19

T7

11

T8

6

values[0x1]

all_enables

biggest_size

1102014

1

T6

4

T7

3

T8

3