Line Coverage for Module :
prim_reg_cdc_arb ( parameter DataWidth=4,ResetVal=9,DstWrReq=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 47 | 94.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 112 | 3 | 3 | 100.00 |
ALWAYS | 122 | 6 | 6 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
ALWAYS | 140 | 6 | 6 | 100.00 |
ALWAYS | 156 | 10 | 9 | 90.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
ALWAYS | 188 | 19 | 17 | 89.47 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
115 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
133 |
1 |
1 |
|
|
|
MISSING_ELSE |
136 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
|
|
|
MISSING_ELSE |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
1 |
1 |
163 |
0 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
|
|
|
MISSING_ELSE |
184 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
0 |
1 |
207 |
0 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
212 |
1 |
1 |
|
|
|
MISSING_ELSE |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
Line Coverage for Module :
prim_reg_cdc_arb ( parameter DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal=28290,DstWrReq=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 300 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
284 |
1 |
1 |
285 |
1 |
1 |
300 |
|
unreachable |
Cond Coverage for Module :
prim_reg_cdc_arb ( parameter DataWidth=4,ResetVal=9,DstWrReq=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 43 | 36 | 83.72 |
Logical | 43 | 36 | 83.72 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T4,T5 |
LINE 124
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9 |
LINE 130
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T5 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Covered | T9 |
LINE 136
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T9 |
LINE 158
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 160
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 162
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Not Covered | |
LINE 184
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T1,T4,T5 |
LINE 208
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 229
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T6,T7,T8 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T4,T5 |
1 | 0 | 0 | Covered | T1,T4,T5 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T7,T8 |
LINE 245
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_reg_cdc_arb ( parameter DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal=28290,DstWrReq=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T6,T7,T8 |
Branch Coverage for Module :
prim_reg_cdc_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
20 |
86.96 |
IF |
112 |
2 |
2 |
100.00 |
IF |
122 |
4 |
4 |
100.00 |
IF |
140 |
4 |
4 |
100.00 |
IF |
156 |
6 |
5 |
83.33 |
CASE |
198 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 112 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 122 if ((!rst_dst_ni))
-2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Covered |
T9 |
0 |
0 |
1 |
Covered |
T9 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_dst_ni))
-2-: 142 if (gen_wr_req.dst_lat_d)
-3-: 144 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 156 if ((!rst_dst_ni))
-2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 164 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 198 case (gen_wr_req.state_q)
-2-: 201 if (gen_wr_req.dst_req)
-3-: 205 if (dst_update)
-4-: 208 if ((dst_qs_o != dst_qs_i))
-5-: 218 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
1 |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
0 |
Covered |
T1,T4,T5 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Module :
prim_reg_cdc_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1316660053 |
0 |
0 |
5040 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1316660053 |
4905 |
0 |
0 |
T1 |
1275428 |
55 |
0 |
0 |
T2 |
298021 |
5 |
0 |
0 |
T3 |
0 |
45 |
0 |
0 |
T4 |
261614 |
0 |
0 |
0 |
T5 |
215786 |
0 |
0 |
0 |
T10 |
0 |
35 |
0 |
0 |
T11 |
0 |
25 |
0 |
0 |
T12 |
0 |
15 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
5 |
0 |
0 |
T15 |
0 |
155 |
0 |
0 |
T16 |
0 |
85 |
0 |
0 |
T17 |
4868 |
0 |
0 |
0 |
T18 |
29988 |
0 |
0 |
0 |
T19 |
19493 |
0 |
0 |
0 |
T20 |
12672 |
0 |
0 |
0 |
T21 |
7281 |
0 |
0 |
0 |
T22 |
24402 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 45 | 90.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 112 | 3 | 3 | 100.00 |
ALWAYS | 122 | 6 | 4 | 66.67 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
ALWAYS | 140 | 6 | 6 | 100.00 |
ALWAYS | 156 | 10 | 9 | 90.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
ALWAYS | 188 | 19 | 17 | 89.47 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
115 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
129 |
0 |
1 |
130 |
1 |
1 |
133 |
0 |
1 |
|
|
|
MISSING_ELSE |
136 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
|
|
|
MISSING_ELSE |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
1 |
1 |
163 |
0 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
|
|
|
MISSING_ELSE |
184 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
0 |
1 |
207 |
0 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
212 |
1 |
1 |
|
|
|
MISSING_ELSE |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
| Total | Covered | Percent |
Conditions | 42 | 32 | 76.19 |
Logical | 42 | 32 | 76.19 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T2 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T4,T2 |
LINE 124
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 130
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T5 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Not Covered | |
LINE 136
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Not Covered | |
LINE 158
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 160
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 162
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Not Covered | |
LINE 184
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T1,T4,T5 |
LINE 208
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 229
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T6,T7,T8 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T4,T5 |
1 | 0 | 0 | Covered | T1,T4,T5 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T7,T8 |
LINE 245
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
18 |
78.26 |
IF |
112 |
2 |
2 |
100.00 |
IF |
122 |
4 |
2 |
50.00 |
IF |
140 |
4 |
4 |
100.00 |
IF |
156 |
6 |
5 |
83.33 |
CASE |
198 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 112 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 122 if ((!rst_dst_ni))
-2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_dst_ni))
-2-: 142 if (gen_wr_req.dst_lat_d)
-3-: 144 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 156 if ((!rst_dst_ni))
-2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 164 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 198 case (gen_wr_req.state_q)
-2-: 201 if (gen_wr_req.dst_req)
-3-: 205 if (dst_update)
-4-: 208 if ((dst_qs_o != dst_qs_i))
-5-: 218 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
1 |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
0 |
Covered |
T1,T4,T5 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395576263 |
0 |
0 |
1008 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395576263 |
981 |
0 |
0 |
T1 |
228534 |
11 |
0 |
0 |
T2 |
90545 |
1 |
0 |
0 |
T3 |
0 |
9 |
0 |
0 |
T4 |
89333 |
0 |
0 |
0 |
T5 |
71158 |
0 |
0 |
0 |
T10 |
0 |
7 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T16 |
0 |
17 |
0 |
0 |
T17 |
1485 |
0 |
0 |
0 |
T18 |
9135 |
0 |
0 |
0 |
T19 |
5946 |
0 |
0 |
0 |
T20 |
3858 |
0 |
0 |
0 |
T21 |
2227 |
0 |
0 |
0 |
T22 |
7067 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 45 | 90.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 112 | 3 | 3 | 100.00 |
ALWAYS | 122 | 6 | 4 | 66.67 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
ALWAYS | 140 | 6 | 6 | 100.00 |
ALWAYS | 156 | 10 | 9 | 90.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
ALWAYS | 188 | 19 | 17 | 89.47 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
115 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
129 |
0 |
1 |
130 |
1 |
1 |
133 |
0 |
1 |
|
|
|
MISSING_ELSE |
136 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
|
|
|
MISSING_ELSE |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
1 |
1 |
163 |
0 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
|
|
|
MISSING_ELSE |
184 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
0 |
1 |
207 |
0 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
212 |
1 |
1 |
|
|
|
MISSING_ELSE |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
| Total | Covered | Percent |
Conditions | 42 | 32 | 76.19 |
Logical | 42 | 32 | 76.19 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T5 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T4,T5 |
LINE 124
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 130
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T5 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Not Covered | |
LINE 136
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Not Covered | |
LINE 158
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 160
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 162
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Not Covered | |
LINE 184
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T1,T4,T5 |
LINE 208
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 229
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T6,T7,T8 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T4,T5 |
1 | 0 | 0 | Covered | T1,T4,T5 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T7,T8 |
LINE 245
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
18 |
78.26 |
IF |
112 |
2 |
2 |
100.00 |
IF |
122 |
4 |
2 |
50.00 |
IF |
140 |
4 |
4 |
100.00 |
IF |
156 |
6 |
5 |
83.33 |
CASE |
198 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 112 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 122 if ((!rst_dst_ni))
-2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_dst_ni))
-2-: 142 if (gen_wr_req.dst_lat_d)
-3-: 144 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 156 if ((!rst_dst_ni))
-2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 164 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 198 case (gen_wr_req.state_q)
-2-: 201 if (gen_wr_req.dst_req)
-3-: 205 if (dst_update)
-4-: 208 if ((dst_qs_o != dst_qs_i))
-5-: 218 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
1 |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
0 |
Covered |
T1,T4,T5 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
196911569 |
0 |
0 |
1008 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
196911569 |
981 |
0 |
0 |
T1 |
113540 |
11 |
0 |
0 |
T2 |
45253 |
1 |
0 |
0 |
T3 |
0 |
9 |
0 |
0 |
T4 |
23036 |
0 |
0 |
0 |
T5 |
23281 |
0 |
0 |
0 |
T10 |
0 |
7 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T16 |
0 |
17 |
0 |
0 |
T17 |
730 |
0 |
0 |
0 |
T18 |
4514 |
0 |
0 |
0 |
T19 |
2920 |
0 |
0 |
0 |
T20 |
1910 |
0 |
0 |
0 |
T21 |
1080 |
0 |
0 |
0 |
T22 |
4295 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 45 | 90.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 112 | 3 | 3 | 100.00 |
ALWAYS | 122 | 6 | 4 | 66.67 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
ALWAYS | 140 | 6 | 6 | 100.00 |
ALWAYS | 156 | 10 | 9 | 90.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
ALWAYS | 188 | 19 | 17 | 89.47 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
115 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
129 |
0 |
1 |
130 |
1 |
1 |
133 |
0 |
1 |
|
|
|
MISSING_ELSE |
136 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
|
|
|
MISSING_ELSE |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
1 |
1 |
163 |
0 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
|
|
|
MISSING_ELSE |
184 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
0 |
1 |
207 |
0 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
212 |
1 |
1 |
|
|
|
MISSING_ELSE |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
| Total | Covered | Percent |
Conditions | 42 | 32 | 76.19 |
Logical | 42 | 32 | 76.19 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T5 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T4,T5 |
LINE 124
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 130
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T5 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Not Covered | |
LINE 136
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Not Covered | |
LINE 158
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 160
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 162
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Not Covered | |
LINE 184
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T1,T4,T5 |
LINE 208
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 229
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T6,T7,T8 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T4,T5 |
1 | 0 | 0 | Covered | T1,T4,T5 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T7,T8 |
LINE 245
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
18 |
78.26 |
IF |
112 |
2 |
2 |
100.00 |
IF |
122 |
4 |
2 |
50.00 |
IF |
140 |
4 |
4 |
100.00 |
IF |
156 |
6 |
5 |
83.33 |
CASE |
198 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 112 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 122 if ((!rst_dst_ni))
-2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_dst_ni))
-2-: 142 if (gen_wr_req.dst_lat_d)
-3-: 144 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 156 if ((!rst_dst_ni))
-2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 164 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 198 case (gen_wr_req.state_q)
-2-: 201 if (gen_wr_req.dst_req)
-3-: 205 if (dst_update)
-4-: 208 if ((dst_qs_o != dst_qs_i))
-5-: 218 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
1 |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
0 |
Covered |
T1,T4,T5 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422761966 |
0 |
0 |
1008 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
422761966 |
981 |
0 |
0 |
T1 |
247064 |
11 |
0 |
0 |
T2 |
94321 |
1 |
0 |
0 |
T3 |
0 |
9 |
0 |
0 |
T4 |
93058 |
0 |
0 |
0 |
T5 |
74125 |
0 |
0 |
0 |
T10 |
0 |
7 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T16 |
0 |
17 |
0 |
0 |
T17 |
1546 |
0 |
0 |
0 |
T18 |
9515 |
0 |
0 |
0 |
T19 |
6194 |
0 |
0 |
0 |
T20 |
4020 |
0 |
0 |
0 |
T21 |
2320 |
0 |
0 |
0 |
T22 |
7361 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 45 | 90.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 112 | 3 | 3 | 100.00 |
ALWAYS | 122 | 6 | 4 | 66.67 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
ALWAYS | 140 | 6 | 6 | 100.00 |
ALWAYS | 156 | 10 | 9 | 90.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
ALWAYS | 188 | 19 | 17 | 89.47 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
115 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
129 |
0 |
1 |
130 |
1 |
1 |
133 |
0 |
1 |
|
|
|
MISSING_ELSE |
136 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
|
|
|
MISSING_ELSE |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
1 |
1 |
163 |
0 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
|
|
|
MISSING_ELSE |
184 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
0 |
1 |
207 |
0 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
212 |
1 |
1 |
|
|
|
MISSING_ELSE |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
| Total | Covered | Percent |
Conditions | 42 | 32 | 76.19 |
Logical | 42 | 32 | 76.19 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T5 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T4,T5 |
LINE 124
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 130
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T5 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Not Covered | |
LINE 136
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Not Covered | |
LINE 158
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 160
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 162
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Not Covered | |
LINE 184
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T1,T4,T5 |
LINE 208
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 229
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T6,T7,T8 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T4,T5 |
1 | 0 | 0 | Covered | T1,T4,T5 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T7,T8 |
LINE 245
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
18 |
78.26 |
IF |
112 |
2 |
2 |
100.00 |
IF |
122 |
4 |
2 |
50.00 |
IF |
140 |
4 |
4 |
100.00 |
IF |
156 |
6 |
5 |
83.33 |
CASE |
198 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 112 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 122 if ((!rst_dst_ni))
-2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_dst_ni))
-2-: 142 if (gen_wr_req.dst_lat_d)
-3-: 144 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 156 if ((!rst_dst_ni))
-2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 164 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 198 case (gen_wr_req.state_q)
-2-: 201 if (gen_wr_req.dst_req)
-3-: 205 if (dst_update)
-4-: 208 if ((dst_qs_o != dst_qs_i))
-5-: 218 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
1 |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
0 |
Covered |
T1,T4,T5 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
202955029 |
0 |
0 |
1008 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
202955029 |
981 |
0 |
0 |
T1 |
118592 |
11 |
0 |
0 |
T2 |
45275 |
1 |
0 |
0 |
T3 |
0 |
9 |
0 |
0 |
T4 |
44669 |
0 |
0 |
0 |
T5 |
35581 |
0 |
0 |
0 |
T10 |
0 |
7 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T16 |
0 |
17 |
0 |
0 |
T17 |
742 |
0 |
0 |
0 |
T18 |
4567 |
0 |
0 |
0 |
T19 |
2973 |
0 |
0 |
0 |
T20 |
1929 |
0 |
0 |
0 |
T21 |
1114 |
0 |
0 |
0 |
T22 |
3533 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 47 | 94.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 112 | 3 | 3 | 100.00 |
ALWAYS | 122 | 6 | 6 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
ALWAYS | 140 | 6 | 6 | 100.00 |
ALWAYS | 156 | 10 | 9 | 90.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
ALWAYS | 188 | 19 | 17 | 89.47 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
115 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
133 |
1 |
1 |
|
|
|
MISSING_ELSE |
136 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
|
|
|
MISSING_ELSE |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
1 |
1 |
163 |
0 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
|
|
|
MISSING_ELSE |
184 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
0 |
1 |
207 |
0 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
212 |
1 |
1 |
|
|
|
MISSING_ELSE |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
| Total | Covered | Percent |
Conditions | 42 | 36 | 85.71 |
Logical | 42 | 36 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T2 |
1 | 1 | Covered | T1,T4,T5 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T4,T5 |
LINE 124
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9 |
LINE 130
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T5 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Covered | T9 |
LINE 136
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T7,T8 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T9 |
LINE 158
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 160
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 162
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Not Covered | |
LINE 184
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T1,T4,T5 |
LINE 208
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 229
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T6,T7,T8 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T1,T4,T5 |
1 | 0 | 0 | Covered | T1,T4,T5 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T7,T8 |
LINE 245
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
20 |
86.96 |
IF |
112 |
2 |
2 |
100.00 |
IF |
122 |
4 |
4 |
100.00 |
IF |
140 |
4 |
4 |
100.00 |
IF |
156 |
6 |
5 |
83.33 |
CASE |
198 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 112 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 122 if ((!rst_dst_ni))
-2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Covered |
T9 |
0 |
0 |
1 |
Covered |
T9 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_dst_ni))
-2-: 142 if (gen_wr_req.dst_lat_d)
-3-: 144 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 156 if ((!rst_dst_ni))
-2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 164 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T6,T7,T8 |
0 |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 198 case (gen_wr_req.state_q)
-2-: 201 if (gen_wr_req.dst_req)
-3-: 205 if (dst_update)
-4-: 208 if ((dst_qs_o != dst_qs_i))
-5-: 218 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T1,T4,T5 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
1 |
Covered |
T1,T4,T5 |
StWait |
- |
- |
- |
0 |
Covered |
T1,T4,T5 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
98455226 |
0 |
0 |
1008 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
98455226 |
981 |
0 |
0 |
T1 |
567698 |
11 |
0 |
0 |
T2 |
22627 |
1 |
0 |
0 |
T3 |
0 |
9 |
0 |
0 |
T4 |
11518 |
0 |
0 |
0 |
T5 |
11641 |
0 |
0 |
0 |
T10 |
0 |
7 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
31 |
0 |
0 |
T16 |
0 |
17 |
0 |
0 |
T17 |
365 |
0 |
0 |
0 |
T18 |
2257 |
0 |
0 |
0 |
T19 |
1460 |
0 |
0 |
0 |
T20 |
955 |
0 |
0 |
0 |
T21 |
540 |
0 |
0 |
0 |
T22 |
2146 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 300 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
284 |
1 |
1 |
285 |
1 |
1 |
300 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T6,T7,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 300 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
284 |
1 |
1 |
285 |
1 |
1 |
300 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T6,T7,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 300 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
284 |
1 |
1 |
285 |
1 |
1 |
300 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T6,T7,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 300 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
284 |
1 |
1 |
285 |
1 |
1 |
300 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T6,T7,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 300 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
284 |
1 |
1 |
285 |
1 |
1 |
300 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T6,T7,T8 |