Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	621693	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3628038

1

T1

43417

T6

274

T7

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1042432	1			T1	11870		T6	579		T7	67
values[0x0]	1472933	1			T1	17198		T6	202		T7	19
values[0x1]	1734366	1			T1	20131		T6	229		T7	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	340680	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3909051

1

T1

46276

T6

541

T7

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15962	1			T1	159		T6	5		T24	2
valid_sources[0x01]	16502	1			T1	170		T6	3		T24	1
valid_sources[0x02]	15387	1			T1	213		T6	1		T24	2
valid_sources[0x03]	16619	1			T1	171		T6	1		T24	5
valid_sources[0x04]	16702	1			T1	204		T6	3		T24	2
valid_sources[0x05]	17814	1			T1	159		T6	3		T24	3
valid_sources[0x06]	18133	1			T1	214		T6	7		T24	2
valid_sources[0x07]	15468	1			T1	200		T6	9		T7	15
valid_sources[0x08]	16572	1			T1	214		T6	4		T24	3
valid_sources[0x09]	16648	1			T1	213		T6	8		T24	1
valid_sources[0x0a]	17040	1			T1	170		T6	5		T24	2
valid_sources[0x0b]	16315	1			T1	200		T6	9		T24	5
valid_sources[0x0c]	16933	1			T1	184		T24	2		T25	11
valid_sources[0x0d]	19349	1			T1	249		T6	9		T24	2
valid_sources[0x0e]	16953	1			T1	173		T6	7		T24	4
valid_sources[0x0f]	15669	1			T1	213		T6	5		T24	3
valid_sources[0x10]	15458	1			T1	165		T6	1		T26	4
valid_sources[0x11]	15179	1			T1	164		T6	2		T24	1
valid_sources[0x12]	17505	1			T1	210		T6	3		T24	2
valid_sources[0x13]	15029	1			T1	228		T6	4		T24	3
valid_sources[0x14]	15578	1			T1	181		T6	1		T24	4
valid_sources[0x15]	17888	1			T1	182		T6	3		T28	3
valid_sources[0x16]	15799	1			T1	182		T6	1		T24	2
valid_sources[0x17]	16938	1			T1	202		T6	7		T24	4
valid_sources[0x18]	16827	1			T1	155		T24	2		T27	1
valid_sources[0x19]	21522	1			T1	232		T6	3		T24	5
valid_sources[0x1a]	17019	1			T1	163		T24	1		T27	3
valid_sources[0x1b]	17350	1			T1	171		T6	3		T24	1
valid_sources[0x1c]	16385	1			T1	174		T6	1		T24	2
valid_sources[0x1d]	15503	1			T1	147		T6	6		T27	2
valid_sources[0x1e]	16598	1			T1	185		T6	1		T24	2
valid_sources[0x1f]	15809	1			T1	175		T27	3		T28	3
valid_sources[0x20]	16716	1			T1	196		T24	1		T25	4
valid_sources[0x21]	17025	1			T1	139		T6	1		T24	2
valid_sources[0x22]	15589	1			T1	193		T24	1		T25	4
valid_sources[0x23]	15665	1			T1	183		T6	1		T24	4
valid_sources[0x24]	16178	1			T1	184		T6	5		T24	2
valid_sources[0x25]	17574	1			T1	217		T6	11		T24	2
valid_sources[0x26]	16947	1			T1	170		T6	4		T23	4
valid_sources[0x27]	15296	1			T1	144		T6	3		T24	2
valid_sources[0x28]	17538	1			T1	189		T24	2		T25	9
valid_sources[0x29]	15689	1			T1	200		T6	12		T24	1
valid_sources[0x2a]	15626	1			T1	195		T6	5		T24	2
valid_sources[0x2b]	16494	1			T1	244		T6	8		T24	1
valid_sources[0x2c]	15952	1			T1	200		T24	5		T27	7
valid_sources[0x2d]	15365	1			T1	167		T6	5		T24	3
valid_sources[0x2e]	16550	1			T1	181		T24	2		T27	4
valid_sources[0x2f]	15200	1			T1	169		T6	5		T24	1
valid_sources[0x30]	16742	1			T1	253		T6	3		T23	1
valid_sources[0x31]	16134	1			T1	208		T6	14		T24	1
valid_sources[0x32]	17712	1			T1	208		T25	11		T27	3
valid_sources[0x33]	15695	1			T1	221		T6	1		T24	3
valid_sources[0x34]	16223	1			T1	224		T6	2		T24	3
valid_sources[0x35]	14956	1			T1	208		T24	1		T27	2
valid_sources[0x36]	18703	1			T1	168		T24	1		T27	2
valid_sources[0x37]	16454	1			T1	189		T6	9		T24	3
valid_sources[0x38]	17598	1			T1	157		T24	4		T26	3
valid_sources[0x39]	15430	1			T1	212		T6	12		T24	2
valid_sources[0x3a]	16750	1			T1	195		T6	15		T24	1
valid_sources[0x3b]	14490	1			T1	189		T6	5		T24	1
valid_sources[0x3c]	16317	1			T1	163		T6	4		T24	1
valid_sources[0x3d]	17360	1			T1	151		T6	1		T27	2
valid_sources[0x3e]	15891	1			T1	203		T6	5		T24	3
valid_sources[0x3f]	16156	1			T1	234		T6	1		T24	3
valid_sources[0x40]	14986	1			T1	159		T6	2		T24	1
valid_sources[0x41]	16760	1			T1	178		T6	12		T24	3
valid_sources[0x42]	18052	1			T1	198		T6	2		T24	6
valid_sources[0x43]	16043	1			T1	159		T6	5		T24	3
valid_sources[0x44]	18544	1			T1	175		T24	3		T27	5
valid_sources[0x45]	16226	1			T1	142		T23	4		T24	3
valid_sources[0x46]	18792	1			T1	179		T24	1		T67	2
valid_sources[0x47]	15754	1			T1	198		T6	10		T24	3
valid_sources[0x48]	16582	1			T1	166		T23	4		T24	3
valid_sources[0x49]	18179	1			T1	192		T6	3		T24	4
valid_sources[0x4a]	17401	1			T1	216		T6	1		T24	3
valid_sources[0x4b]	17089	1			T1	173		T6	5		T24	1
valid_sources[0x4c]	15723	1			T1	176		T6	13		T24	2
valid_sources[0x4d]	15362	1			T1	201		T6	6		T24	3
valid_sources[0x4e]	16253	1			T1	210		T6	11		T24	3
valid_sources[0x4f]	16443	1			T1	195		T6	5		T24	1
valid_sources[0x50]	16406	1			T1	215		T6	5		T24	1
valid_sources[0x51]	18201	1			T1	160		T6	3		T27	2
valid_sources[0x52]	16667	1			T1	203		T6	2		T24	1
valid_sources[0x53]	15456	1			T1	175		T6	2		T24	2
valid_sources[0x54]	16297	1			T1	203		T6	7		T24	4
valid_sources[0x55]	16003	1			T1	190		T6	5		T24	3
valid_sources[0x56]	16792	1			T1	205		T6	2		T24	4
valid_sources[0x57]	15285	1			T1	231		T6	26		T24	1
valid_sources[0x58]	18128	1			T1	169		T6	1		T24	2
valid_sources[0x59]	15365	1			T1	206		T6	3		T24	3
valid_sources[0x5a]	15295	1			T1	211		T6	4		T25	3
valid_sources[0x5b]	15140	1			T1	186		T6	8		T24	3
valid_sources[0x5c]	16191	1			T1	223		T6	2		T27	1
valid_sources[0x5d]	17236	1			T1	194		T6	1		T7	2
valid_sources[0x5e]	14515	1			T1	194		T6	1		T26	16
valid_sources[0x5f]	15552	1			T1	203		T25	4		T27	4
valid_sources[0x60]	17842	1			T1	198		T6	8		T24	2
valid_sources[0x61]	16816	1			T1	187		T6	1		T27	3
valid_sources[0x62]	16465	1			T1	196		T6	3		T24	1
valid_sources[0x63]	16169	1			T1	193		T24	1		T25	4
valid_sources[0x64]	17611	1			T1	199		T24	2		T25	1
valid_sources[0x65]	17119	1			T1	149		T6	1		T7	2
valid_sources[0x66]	17319	1			T1	193		T6	18		T25	11
valid_sources[0x67]	17317	1			T1	162		T24	2		T25	1
valid_sources[0x68]	16146	1			T1	204		T24	3		T28	2
valid_sources[0x69]	16304	1			T1	187		T6	3		T24	1
valid_sources[0x6a]	15664	1			T1	209		T6	3		T27	2
valid_sources[0x6b]	16356	1			T1	159		T6	2		T24	2
valid_sources[0x6c]	16843	1			T1	190		T6	14		T7	4
valid_sources[0x6d]	15495	1			T1	173		T6	5		T25	17
valid_sources[0x6e]	18603	1			T1	177		T6	3		T24	2
valid_sources[0x6f]	17833	1			T1	190		T6	4		T24	1
valid_sources[0x70]	15793	1			T1	187		T6	6		T27	3
valid_sources[0x71]	18439	1			T1	224		T6	5		T24	1
valid_sources[0x72]	17484	1			T1	204		T27	2		T28	2
valid_sources[0x73]	16824	1			T1	215		T6	13		T24	1
valid_sources[0x74]	15132	1			T1	194		T6	4		T24	2
valid_sources[0x75]	15091	1			T1	190		T6	4		T24	1
valid_sources[0x76]	15356	1			T1	240		T24	3		T28	2
valid_sources[0x77]	17280	1			T1	164		T6	6		T24	3
valid_sources[0x78]	16075	1			T1	195		T6	3		T24	1
valid_sources[0x79]	16471	1			T1	217		T6	13		T24	4
valid_sources[0x7a]	15921	1			T1	198		T6	3		T24	1
valid_sources[0x7b]	16584	1			T1	223		T6	7		T24	4
valid_sources[0x7c]	16942	1			T1	187		T24	2		T25	7
valid_sources[0x7d]	15876	1			T1	195		T6	2		T7	8
valid_sources[0x7e]	15067	1			T1	217		T6	1		T25	5
valid_sources[0x7f]	15821	1			T1	166		T6	9		T24	2
valid_sources[0x80]	16699	1			T1	186		T24	3		T27	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

915321

1

T1

10839

T6

70

T7

3

values[0x0]

all_enables

biggest_size

1378786

1

T1

16488

T6

128

T7

11

values[0x1]

all_enables

biggest_size

1333931

1

T1

16090

T6

76

T7

6