Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	769245900	77738	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769245900	77738	0	0
T1	658250	318	0	0
T2	4815485	669	0	0
T3	277470	110	0	0
T4	245125	0	0	0
T11	558490	191	0	0
T12	172885	187	0	0
T13	0	299	0	0
T14	0	713	0	0
T15	0	1507	0	0
T16	0	172	0	0
T17	0	1487	0	0
T18	14665	0	0	0
T19	40375	0	0	0
T20	9345	0	0	0
T21	8330	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153849180	11549	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	11549	0	0
T1	131650	47	0	0
T2	963097	87	0	0
T3	55494	14	0	0
T4	49025	0	0	0
T11	111698	26	0	0
T12	34577	30	0	0
T13	0	40	0	0
T14	0	92	0	0
T15	0	197	0	0
T16	0	27	0	0
T17	0	215	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153849180	15655	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	15655	0	0
T1	131650	64	0	0
T2	963097	136	0	0
T3	55494	21	0	0
T4	49025	0	0	0
T11	111698	41	0	0
T12	34577	38	0	0
T13	0	61	0	0
T14	0	142	0	0
T15	0	308	0	0
T16	0	35	0	0
T17	0	297	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153849180	23764	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	23764	0	0
T1	131650	105	0	0
T2	963097	224	0	0
T3	55494	38	0	0
T4	49025	0	0	0
T11	111698	60	0	0
T12	34577	52	0	0
T13	0	100	0	0
T14	0	244	0	0
T15	0	505	0	0
T16	0	46	0	0
T17	0	466	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153849180	11238	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	11238	0	0
T1	131650	41	0	0
T2	963097	84	0	0
T3	55494	14	0	0
T4	49025	0	0	0
T11	111698	25	0	0
T12	34577	29	0	0
T13	0	37	0	0
T14	0	88	0	0
T15	0	193	0	0
T16	0	28	0	0
T17	0	212	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153849180	15532	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	15532	0	0
T1	131650	61	0	0
T2	963097	138	0	0
T3	55494	23	0	0
T4	49025	0	0	0
T11	111698	39	0	0
T12	34577	38	0	0
T13	0	61	0	0
T14	0	147	0	0
T15	0	304	0	0
T16	0	36	0	0
T17	0	297	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0