Unified Coverage Report :: Module :: prim_generic_clock_buf

Module : prim_generic_clock_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_div_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_div_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_div4_powerup_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_aon_powerup_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_powerup_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_powerup_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_usb_powerup_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_div2_powerup_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_aon_secure_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_aon_peri_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_aon_timers_buf.gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_div_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_div_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_div_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_div_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_io_div4_powerup_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_io_div4_powerup_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_aon_powerup_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_aon_powerup_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_powerup_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_main_powerup_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_io_powerup_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_io_powerup_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_usb_powerup_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_usb_powerup_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_io_div2_powerup_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_io_div2_powerup_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_aon_secure_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_aon_secure_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_aon_peri_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_aon_peri_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_aon_timers_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_aon_timers_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_buf

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_div_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_div_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_clk_io_div4_powerup_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_clk_aon_powerup_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_clk_main_powerup_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_clk_io_powerup_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_clk_usb_powerup_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_clk_io_div2_powerup_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_clk_aon_secure_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_clk_aon_peri_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1

Line Coverage for Instance : tb.dut.u_clk_aon_timers_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
21	1	1