Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	153849180	151263854	0	0
AllClkBypReqTrue_A	153849180	134300	0	0
IoClkBypReqFalse_A	153849180	151178448	0	2403
IoClkBypReqTrue_A	153849180	215182	0	0
LcClkBypAckFalse_A	153849180	151271817	0	0
LcClkBypAckTrue_A	153849180	126337	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	151263854	0	0
T1	131650	129967	0	0
T2	963097	960463	0	0
T3	55494	55339	0	0
T4	49025	3904	0	0
T5	10693	10673	0	0
T11	111698	111637	0	0
T18	2933	2701	0	0
T19	8075	8012	0	0
T20	1869	1797	0	0
T21	1666	1628	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	134300	0	0
T1	131650	456	0	0
T2	963097	566	0	0
T3	55494	0	0	0
T4	49025	0	0	0
T11	111698	0	0	0
T12	34577	0	0	0
T15	0	54	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0
T30	0	73	0	0
T42	0	222	0	0
T99	0	31	0	0
T100	0	259	0	0
T101	0	182	0	0
T102	0	7	0	0
T103	0	179	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	151178448	0	2403
T1	131650	129922	0	3
T2	963097	960282	0	3
T3	55494	55337	0	3
T4	49025	3870	0	3
T5	10693	10671	0	3
T11	111698	111635	0	3
T18	2933	2699	0	3
T19	8075	8010	0	3
T20	1869	1795	0	3
T21	1666	1626	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	215182	0	0
T1	131650	893	0	0
T2	963097	723	0	0
T3	55494	0	0	0
T4	49025	0	0	0
T11	111698	0	0	0
T12	34577	0	0	0
T15	0	118	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0
T42	0	34	0	0
T99	0	31	0	0
T100	0	556	0	0
T101	0	326	0	0
T102	0	68	0	0
T103	0	264	0	0
T104	0	85	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	151271817	0	0
T1	131650	129970	0	0
T2	963097	960595	0	0
T3	55494	55339	0	0
T4	49025	3904	0	0
T5	10693	10673	0	0
T11	111698	111637	0	0
T18	2933	2701	0	0
T19	8075	8012	0	0
T20	1869	1797	0	0
T21	1666	1628	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	126337	0	0
T1	131650	429	0	0
T2	963097	434	0	0
T3	55494	0	0	0
T4	49025	0	0	0
T11	111698	0	0	0
T12	34577	0	0	0
T15	0	56	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0
T42	0	31	0	0
T99	0	27	0	0
T100	0	352	0	0
T101	0	152	0	0
T102	0	54	0	0
T103	0	202	0	0
T104	0	77	0	0