Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T2
01CoveredT1,T5,T2
10CoveredT1,T2,T30 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T2
10CoveredT1,T2,T30
11CoveredT1,T2,T30 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T30
10CoveredT1,T5,T2
11CoveredT1,T5,T2
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 519254943 519252540 0 0
selKnown1 1251179055 1251176652 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 519254943 519252540 0 0
T1 1547204 1547201 0 0
T2 1122034 1122031 0 0
T3 67197 67194 0 0
T4 62932 62929 0 0
T5 40273 40270 0 0
T11 154010 154007 0 0
T18 3515 3512 0 0
T19 41975 41972 0 0
T20 6518 6515 0 0
T21 10412 10409 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1251179055 1251176652 0 0
T1 374205 374202 0 0
T2 2694888 2694885 0 0
T3 161430 161427 0 0
T4 282378 282375 0 0
T5 96771 96768 0 0
T11 369738 369735 0 0
T18 8799 8796 0 0
T19 101100 101097 0 0
T20 15843 15840 0 0
T21 25266 25263 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T2
01CoveredT1,T5,T2
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T2
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T5,T2
11CoveredT1,T5,T2
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 207818241 207817440 0 0
selKnown1 417059685 417058884 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 207818241 207817440 0 0
T1 618991 618990 0 0
T2 448922 448921 0 0
T3 26879 26878 0 0
T4 25172 25171 0 0
T5 16109 16108 0 0
T11 61604 61603 0 0
T18 1406 1405 0 0
T19 16790 16789 0 0
T20 2607 2606 0 0
T21 4165 4164 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 417059685 417058884 0 0
T1 124735 124734 0 0
T2 898296 898295 0 0
T3 53810 53809 0 0
T4 94126 94125 0 0
T5 32257 32256 0 0
T11 123246 123245 0 0
T18 2933 2932 0 0
T19 33700 33699 0 0
T20 5281 5280 0 0
T21 8422 8421 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T2
01CoveredT1,T5,T2
10CoveredT1,T2,T30 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T2
10CoveredT1,T2,T30
11CoveredT1,T2,T30 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T30
10CoveredT1,T5,T2
11CoveredT1,T5,T2
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 207528208 207527407 0 0
selKnown1 417059685 417058884 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 207528208 207527407 0 0
T1 618720 618719 0 0
T2 448651 448650 0 0
T3 26879 26878 0 0
T4 25172 25171 0 0
T5 16109 16108 0 0
T11 61604 61603 0 0
T18 1406 1405 0 0
T19 16790 16789 0 0
T20 2607 2606 0 0
T21 4165 4164 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 417059685 417058884 0 0
T1 124735 124734 0 0
T2 898296 898295 0 0
T3 53810 53809 0 0
T4 94126 94125 0 0
T5 32257 32256 0 0
T11 123246 123245 0 0
T18 2933 2932 0 0
T19 33700 33699 0 0
T20 5281 5280 0 0
T21 8422 8421 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T2
01CoveredT1,T5,T2
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T2
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T5,T2
11CoveredT1,T5,T2
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 103908494 103907693 0 0
selKnown1 417059685 417058884 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 103908494 103907693 0 0
T1 309493 309492 0 0
T2 224461 224460 0 0
T3 13439 13438 0 0
T4 12588 12587 0 0
T5 8055 8054 0 0
T11 30802 30801 0 0
T18 703 702 0 0
T19 8395 8394 0 0
T20 1304 1303 0 0
T21 2082 2081 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 417059685 417058884 0 0
T1 124735 124734 0 0
T2 898296 898295 0 0
T3 53810 53809 0 0
T4 94126 94125 0 0
T5 32257 32256 0 0
T11 123246 123245 0 0
T18 2933 2932 0 0
T19 33700 33699 0 0
T20 5281 5280 0 0
T21 8422 8421 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%