Unified Coverage Report :: Module :: clkmgr_extclk_sva_if

Module : clkmgr_extclk_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_extclk_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_extclk_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_extclk_sva_if

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	34	1	1	100.00
ALWAYS	49	1	1	100.00
ALWAYS	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
49	1	1
66	1	1

---

Cond Coverage for Module : clkmgr_extclk_sva_if

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (lc_clk_byp_req_i == On)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T30
1	Covered	T1,T2,T42

 LINE       49
 EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (lc_hw_debug_en_i == On))
             ---------------1--------------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T30
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

 LINE       49
 SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T30
1	Covered	T1,T2,T30

 LINE       49
 SUB-EXPRESSION (lc_hw_debug_en_i == On)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T30
1	Covered	T1,T2,T30

 LINE       66
 EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (extclk_ctrl_hi_speed_sel == MuBi4True) && (lc_hw_debug_en_i == On))
             ---------------1--------------    -------------------2-------------------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T30
1	0	1	Covered	T1,T2,T30
1	1	0	Covered	T1,T2,T30
1	1	1	Covered	T1,T2,T30

 LINE       66
 SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T30

 LINE       66
 SUB-EXPRESSION (extclk_ctrl_hi_speed_sel == MuBi4True)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       66
 SUB-EXPRESSION (lc_hw_debug_en_i == On)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T30

---

Assert Coverage for Module : clkmgr_extclk_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFall_A	153849180	4406	0	0
AllClkBypReqRise_A	153849180	4408	0	0
HiSpeedSelFall_A	153849180	2652	0	0
HiSpeedSelRise_A	153849180	2653	0	0
IoClkBypReqFall_A	153849180	5584	0	0
IoClkBypReqRise_A	153849180	5586	0	0

AllClkBypReqFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	4406	0	0
T1	131650	19	0	0
T2	963097	19	0	0
T3	55494	0	0	0
T4	49025	0	0	0
T11	111698	0	0	0
T12	34577	0	0	0
T15	0	3	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0
T30	0	9	0	0
T42	0	11	0	0
T99	0	2	0	0
T100	0	8	0	0
T101	0	6	0	0
T102	0	1	0	0
T103	0	7	0	0

AllClkBypReqRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	4408	0	0
T1	131650	19	0	0
T2	963097	19	0	0
T3	55494	0	0	0
T4	49025	0	0	0
T11	111698	0	0	0
T12	34577	0	0	0
T15	0	3	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0
T30	0	9	0	0
T42	0	11	0	0
T99	0	2	0	0
T100	0	8	0	0
T101	0	6	0	0
T102	0	1	0	0
T103	0	7	0	0

HiSpeedSelFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	2652	0	0
T1	131650	13	0	0
T2	963097	11	0	0
T3	55494	0	0	0
T4	49025	0	0	0
T11	111698	0	0	0
T12	34577	0	0	0
T15	0	3	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0
T30	0	7	0	0
T42	0	7	0	0
T99	0	1	0	0
T100	0	6	0	0
T101	0	3	0	0
T102	0	1	0	0
T103	0	6	0	0

HiSpeedSelRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	2653	0	0
T1	131650	13	0	0
T2	963097	11	0	0
T3	55494	0	0	0
T4	49025	0	0	0
T11	111698	0	0	0
T12	34577	0	0	0
T15	0	3	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0
T30	0	7	0	0
T42	0	7	0	0
T99	0	1	0	0
T100	0	6	0	0
T101	0	3	0	0
T102	0	1	0	0
T103	0	6	0	0

IoClkBypReqFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	5584	0	0
T1	131650	29	0	0
T2	963097	20	0	0
T3	55494	0	0	0
T4	49025	0	0	0
T11	111698	0	0	0
T12	34577	0	0	0
T15	0	4	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0
T42	0	1	0	0
T99	0	1	0	0
T100	0	14	0	0
T101	0	12	0	0
T102	0	3	0	0
T103	0	6	0	0
T104	0	2	0	0

IoClkBypReqRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153849180	5586	0	0
T1	131650	29	0	0
T2	963097	20	0	0
T3	55494	0	0	0
T4	49025	0	0	0
T11	111698	0	0	0
T12	34577	0	0	0
T15	0	4	0	0
T18	2933	0	0	0
T19	8075	0	0	0
T20	1869	0	0	0
T21	1666	0	0	0
T42	0	1	0	0
T99	0	1	0	0
T100	0	14	0	0
T101	0	12	0	0
T102	0	3	0	0
T103	0	6	0	0
T104	0	2	0	0