Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	154776423	5341245	0	0
clk_enables_rd_A	154776423	21142	0	0
clk_hints_rd_A	154776423	18315	0	0
extclk_ctrl_rd_A	154776423	25425	0	0
extclk_ctrl_regwen_rd_A	154776423	17399	0	0
jitter_enable_rd_A	154776423	27296	0	0
jitter_regwen_rd_A	154776423	19842	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154776423	5341245	0	0
T1	131650	65502	0	0
T6	8620	9	0	0
T23	1177	2	0	0
T24	4951	6	0	0
T41	1646	70	0	0
T67	5632	4	0	0
T68	1135	16	0	0
T69	22689	2	0	0
T75	13069	5	0	0
T81	12377	7	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154776423	21142	0	0
T7	2081	7	0	0
T23	1177	1	0	0
T24	4951	99	0	0
T25	9413	212	0	0
T27	10230	206	0	0
T59	1255	5	0	0
T64	0	162	0	0
T65	11135	0	0	0
T79	1004	5	0	0
T83	6472	44	0	0
T84	1343	0	0	0
T85	0	21	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154776423	18315	0	0
T7	2081	1	0	0
T23	1177	14	0	0
T24	4951	112	0	0
T25	9413	245	0	0
T27	10230	291	0	0
T59	1255	6	0	0
T62	0	59	0	0
T64	0	108	0	0
T65	11135	0	0	0
T83	6472	71	0	0
T84	1343	0	0	0
T85	1095	7	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154776423	25425	0	0
T23	1177	3	0	0
T25	9413	22	0	0
T27	10230	36	0	0
T62	0	60	0	0
T64	0	29	0	0
T65	11135	0	0	0
T70	0	33	0	0
T79	1004	5	0	0
T83	6472	51	0	0
T84	1343	0	0	0
T85	1095	0	0	0
T86	506	0	0	0
T125	575	0	0	0
T132	0	5	0	0
T133	0	15	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154776423	17399	0	0
T7	2081	1	0	0
T23	1177	5	0	0
T24	4951	38	0	0
T25	9413	106	0	0
T27	10230	119	0	0
T59	1255	6	0	0
T64	0	52	0	0
T65	11135	0	0	0
T79	1004	6	0	0
T83	6472	93	0	0
T84	1343	0	0	0
T85	0	2	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154776423	27296	0	0
T7	2081	7	0	0
T23	1177	4	0	0
T24	4951	46	0	0
T25	9413	88	0	0
T27	10230	110	0	0
T59	1255	2	0	0
T64	0	61	0	0
T65	11135	0	0	0
T79	1004	3	0	0
T83	6472	73	0	0
T84	1343	0	0	0
T85	0	4	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154776423	19842	0	0
T23	1177	3	0	0
T24	4951	37	0	0
T25	9413	94	0	0
T27	10230	114	0	0
T59	1255	2	0	0
T62	0	71	0	0
T64	0	47	0	0
T65	11135	0	0	0
T68	0	13	0	0
T83	6472	75	0	0
T84	1343	0	0	0
T85	1095	10	0	0
T86	506	0	0	0