Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	417060115	4702	0	0
g_div2.Div2Whole_A	417060115	5619	0	0
g_div4.Div4Stepped_A	207818643	4605	0	0
g_div4.Div4Whole_A	207818643	5319	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417060115	4702	0	0
T1	124735	17	0	0
T2	898297	13	0	0
T3	53811	0	0	0
T4	94126	0	0	0
T11	123246	0	0	0
T12	138308	0	0	0
T15	0	2	0	0
T18	2934	0	0	0
T19	33701	0	0	0
T20	5281	0	0	0
T21	8423	0	0	0
T30	0	5	0	0
T42	0	2	0	0
T99	0	2	0	0
T100	0	11	0	0
T101	0	8	0	0
T102	0	4	0	0
T103	0	10	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417060115	5619	0	0
T1	124735	25	0	0
T2	898297	20	0	0
T3	53811	0	0	0
T4	94126	0	0	0
T11	123246	0	0	0
T12	138308	0	0	0
T15	0	4	0	0
T18	2934	0	0	0
T19	33701	0	0	0
T20	5281	0	0	0
T21	8423	0	0	0
T30	0	5	0	0
T42	0	9	0	0
T99	0	2	0	0
T100	0	13	0	0
T101	0	9	0	0
T102	0	4	0	0
T103	0	10	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207818643	4605	0	0
T1	618992	15	0	0
T2	448922	13	0	0
T3	26879	0	0	0
T4	25172	0	0	0
T11	61604	0	0	0
T12	69115	0	0	0
T15	0	2	0	0
T18	1407	0	0	0
T19	16790	0	0	0
T20	2608	0	0	0
T21	4165	0	0	0
T30	0	5	0	0
T42	0	1	0	0
T99	0	2	0	0
T100	0	11	0	0
T101	0	8	0	0
T102	0	4	0	0
T103	0	10	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207818643	5319	0	0
T1	618992	19	0	0
T2	448922	18	0	0
T3	26879	0	0	0
T4	25172	0	0	0
T11	61604	0	0	0
T12	69115	0	0	0
T15	0	4	0	0
T18	1407	0	0	0
T19	16790	0	0	0
T20	2608	0	0	0
T21	4165	0	0	0
T30	0	4	0	0
T42	0	9	0	0
T99	0	2	0	0
T100	0	13	0	0
T101	0	9	0	0
T102	0	4	0	0
T103	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	417060115	4702	0	0
g_div2.Div2Whole_A	417060115	5619	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417060115	4702	0	0
T1	124735	17	0	0
T2	898297	13	0	0
T3	53811	0	0	0
T4	94126	0	0	0
T11	123246	0	0	0
T12	138308	0	0	0
T15	0	2	0	0
T18	2934	0	0	0
T19	33701	0	0	0
T20	5281	0	0	0
T21	8423	0	0	0
T30	0	5	0	0
T42	0	2	0	0
T99	0	2	0	0
T100	0	11	0	0
T101	0	8	0	0
T102	0	4	0	0
T103	0	10	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417060115	5619	0	0
T1	124735	25	0	0
T2	898297	20	0	0
T3	53811	0	0	0
T4	94126	0	0	0
T11	123246	0	0	0
T12	138308	0	0	0
T15	0	4	0	0
T18	2934	0	0	0
T19	33701	0	0	0
T20	5281	0	0	0
T21	8423	0	0	0
T30	0	5	0	0
T42	0	9	0	0
T99	0	2	0	0
T100	0	13	0	0
T101	0	9	0	0
T102	0	4	0	0
T103	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T2,T30
1	1	Covered	T1,T2,T30

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	207818643	4605	0	0
g_div4.Div4Whole_A	207818643	5319	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207818643	4605	0	0
T1	618992	15	0	0
T2	448922	13	0	0
T3	26879	0	0	0
T4	25172	0	0	0
T11	61604	0	0	0
T12	69115	0	0	0
T15	0	2	0	0
T18	1407	0	0	0
T19	16790	0	0	0
T20	2608	0	0	0
T21	4165	0	0	0
T30	0	5	0	0
T42	0	1	0	0
T99	0	2	0	0
T100	0	11	0	0
T101	0	8	0	0
T102	0	4	0	0
T103	0	10	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207818643	5319	0	0
T1	618992	19	0	0
T2	448922	18	0	0
T3	26879	0	0	0
T4	25172	0	0	0
T11	61604	0	0	0
T12	69115	0	0	0
T15	0	4	0	0
T18	1407	0	0	0
T19	16790	0	0	0
T20	2608	0	0	0
T21	4165	0	0	0
T30	0	4	0	0
T42	0	9	0	0
T99	0	2	0	0
T100	0	13	0	0
T101	0	9	0	0
T102	0	4	0	0
T103	0	10	0	0