Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	45926	0	0
CgEnOn_A	2147483647	36860	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45926	0	0
T1	1187959	240	0	0
T2	2555434	52	0	0
T3	150181	3	0	0
T4	229937	51	0	0
T5	56421	3	0	0
T11	344037	3	0	0
T12	144076	0	0	0
T13	432495	0	0	0
T18	8098	6	0	0
T19	93991	3	0	0
T20	14693	9	0	0
T21	23443	7	0	0
T30	14886	0	0	0
T33	2818	0	0	0
T37	3128	6	0	0
T38	9662	12	0	0
T39	21406	6	0	0
T40	0	5	0	0
T42	5771	0	0	0
T49	0	15	0	0
T99	10236	0	0	0
T100	10923	0	0	0
T105	0	6	0	0
T106	15177	0	0	0
T134	0	5	0	0
T135	0	25	0	0
T136	0	10	0	0
T137	0	20	0	0
T138	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36860	0	0
T1	2238943	261	0	0
T2	5973149	20	0	0
T3	345246	0	0	0
T4	571155	0	0	0
T11	790817	0	0	0
T12	887442	0	0	0
T13	832995	0	0	0
T18	18733	7	0	0
T19	216160	0	0	0
T20	33836	12	0	0
T21	53977	5	0	0
T30	28224	0	0	0
T33	5520	0	0	0
T37	6118	11	0	0
T38	18518	22	0	0
T39	40590	11	0	0
T40	0	6	0	0
T42	11085	0	0	0
T49	0	18	0	0
T99	19592	0	0	0
T100	20249	0	0	0
T105	0	11	0	0
T106	29337	5	0	0
T107	0	3	0	0
T134	0	7	0	0
T135	0	29	0	0
T136	0	12	0	0
T137	0	23	0	0
T138	0	10	0	0
T139	0	2	0	0
T143	0	24	0	0
T144	0	46	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207818241	153	0	0
CgEnOn_A	207818241	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207818241	153	0	0
T13	96105	0	0	0
T30	3394	0	0	0
T33	609	0	0	0
T37	675	1	0	0
T38	2133	2	0	0
T39	4730	1	0	0
T40	0	1	0	0
T42	1288	0	0	0
T49	0	3	0	0
T99	2298	0	0	0
T100	2580	0	0	0
T106	3352	0	0	0
T134	0	1	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207818241	153	0	0
T13	96105	0	0	0
T30	3394	0	0	0
T33	609	0	0	0
T37	675	1	0	0
T38	2133	2	0	0
T39	4730	1	0	0
T40	0	1	0	0
T42	1288	0	0	0
T49	0	3	0	0
T99	2298	0	0	0
T100	2580	0	0	0
T106	3352	0	0	0
T134	0	1	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103908494	153	0	0
CgEnOn_A	103908494	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103908494	153	0	0
T13	48052	0	0	0
T30	1697	0	0	0
T33	304	0	0	0
T37	337	1	0	0
T38	1066	2	0	0
T39	2365	1	0	0
T40	0	1	0	0
T42	644	0	0	0
T49	0	3	0	0
T99	1149	0	0	0
T100	1289	0	0	0
T106	1676	0	0	0
T134	0	1	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103908494	153	0	0
T13	48052	0	0	0
T30	1697	0	0	0
T33	304	0	0	0
T37	337	1	0	0
T38	1066	2	0	0
T39	2365	1	0	0
T40	0	1	0	0
T42	644	0	0	0
T49	0	3	0	0
T99	1149	0	0	0
T100	1289	0	0	0
T106	1676	0	0	0
T134	0	1	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	417059685	153	0	0
CgEnOn_A	417059685	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417059685	153	0	0
T13	192234	0	0	0
T30	6401	0	0	0
T33	1297	0	0	0
T37	1442	1	0	0
T38	4331	2	0	0
T39	9581	1	0	0
T40	0	1	0	0
T42	2551	0	0	0
T49	0	3	0	0
T99	4491	0	0	0
T100	4476	0	0	0
T106	6797	0	0	0
T134	0	1	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417059685	148	0	0
T13	192234	0	0	0
T30	6401	0	0	0
T33	1297	0	0	0
T37	1442	1	0	0
T38	4331	2	0	0
T39	9581	1	0	0
T40	0	1	0	0
T42	2551	0	0	0
T49	0	3	0	0
T99	4491	0	0	0
T100	4476	0	0	0
T106	6797	0	0	0
T134	0	1	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445361918	139	0	0
CgEnOn_A	445361918	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	139	0	0
T13	200250	0	0	0
T30	6669	0	0	0
T33	1351	0	0	0
T37	1495	1	0	0
T38	4428	2	0	0
T39	9592	1	0	0
T40	0	1	0	0
T42	2657	0	0	0
T49	0	3	0	0
T99	4678	0	0	0
T100	4663	0	0	0
T106	7080	0	0	0
T134	0	2	0	0
T135	0	4	0	0
T136	0	2	0	0
T137	0	3	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	133	0	0
T13	200250	0	0	0
T30	6669	0	0	0
T33	1351	0	0	0
T37	1495	1	0	0
T38	4428	2	0	0
T39	9592	1	0	0
T40	0	1	0	0
T42	2657	0	0	0
T49	0	3	0	0
T99	4678	0	0	0
T100	4663	0	0	0
T106	7080	0	0	0
T134	0	2	0	0
T135	0	4	0	0
T136	0	2	0	0
T137	0	3	0	0
T139	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103908494	153	0	0
CgEnOn_A	103908494	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103908494	153	0	0
T13	48052	0	0	0
T30	1697	0	0	0
T33	304	0	0	0
T37	337	1	0	0
T38	1066	2	0	0
T39	2365	1	0	0
T40	0	1	0	0
T42	644	0	0	0
T49	0	3	0	0
T99	1149	0	0	0
T100	1289	0	0	0
T106	1676	0	0	0
T134	0	1	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103908494	153	0	0
T13	48052	0	0	0
T30	1697	0	0	0
T33	304	0	0	0
T37	337	1	0	0
T38	1066	2	0	0
T39	2365	1	0	0
T40	0	1	0	0
T42	644	0	0	0
T49	0	3	0	0
T99	1149	0	0	0
T100	1289	0	0	0
T106	1676	0	0	0
T134	0	1	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445361918	139	0	0
CgEnOn_A	445361918	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	139	0	0
T13	200250	0	0	0
T30	6669	0	0	0
T33	1351	0	0	0
T37	1495	1	0	0
T38	4428	2	0	0
T39	9592	1	0	0
T40	0	1	0	0
T42	2657	0	0	0
T49	0	3	0	0
T99	4678	0	0	0
T100	4663	0	0	0
T106	7080	0	0	0
T134	0	2	0	0
T135	0	4	0	0
T136	0	2	0	0
T137	0	3	0	0
T145	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	133	0	0
T13	200250	0	0	0
T30	6669	0	0	0
T33	1351	0	0	0
T37	1495	1	0	0
T38	4428	2	0	0
T39	9592	1	0	0
T40	0	1	0	0
T42	2657	0	0	0
T49	0	3	0	0
T99	4678	0	0	0
T100	4663	0	0	0
T106	7080	0	0	0
T134	0	2	0	0
T135	0	4	0	0
T136	0	2	0	0
T137	0	3	0	0
T139	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103908494	153	0	0
CgEnOn_A	103908494	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103908494	153	0	0
T13	48052	0	0	0
T30	1697	0	0	0
T33	304	0	0	0
T37	337	1	0	0
T38	1066	2	0	0
T39	2365	1	0	0
T40	0	1	0	0
T42	644	0	0	0
T49	0	3	0	0
T99	1149	0	0	0
T100	1289	0	0	0
T106	1676	0	0	0
T134	0	1	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103908494	153	0	0
T13	48052	0	0	0
T30	1697	0	0	0
T33	304	0	0	0
T37	337	1	0	0
T38	1066	2	0	0
T39	2365	1	0	0
T40	0	1	0	0
T42	644	0	0	0
T49	0	3	0	0
T99	1149	0	0	0
T100	1289	0	0	0
T106	1676	0	0	0
T134	0	1	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207818241	7386	0	0
CgEnOn_A	207818241	5130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207818241	7386	0	0
T1	618991	69	0	0
T2	448922	16	0	0
T3	26879	1	0	0
T4	25172	17	0	0
T5	16109	1	0	0
T11	61604	1	0	0
T18	1406	1	0	0
T19	16790	1	0	0
T20	2607	1	0	0
T21	4165	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207818241	5130	0	0
T1	618991	63	0	0
T2	448922	4	0	0
T3	26879	0	0	0
T4	25172	0	0	0
T11	61604	0	0	0
T12	69115	0	0	0
T18	1406	0	0	0
T19	16790	0	0	0
T20	2607	0	0	0
T21	4165	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	8	0	0
T144	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103908494	6920	0	0
CgEnOn_A	103908494	4668	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103908494	6920	0	0
T1	309493	48	0	0
T2	224461	16	0	0
T3	13439	1	0	0
T4	12588	17	0	0
T5	8055	1	0	0
T11	30802	1	0	0
T18	703	1	0	0
T19	8395	1	0	0
T20	1304	1	0	0
T21	2082	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103908494	4668	0	0
T1	309493	42	0	0
T2	224461	4	0	0
T3	13439	0	0	0
T4	12588	0	0	0
T11	30802	0	0	0
T12	34557	0	0	0
T18	703	0	0	0
T19	8395	0	0	0
T20	1304	0	0	0
T21	2082	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	9	0	0
T144	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	417059685	7575	0	0
CgEnOn_A	417059685	5314	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417059685	7575	0	0
T1	124735	83	0	0
T2	898296	16	0	0
T3	53810	1	0	0
T4	94126	17	0	0
T5	32257	1	0	0
T11	123246	1	0	0
T18	2933	1	0	0
T19	33700	1	0	0
T20	5281	1	0	0
T21	8422	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417059685	5314	0	0
T1	124735	77	0	0
T2	898296	4	0	0
T3	53810	0	0	0
T4	94126	0	0	0
T11	123246	0	0	0
T12	138308	0	0	0
T18	2933	0	0	0
T19	33700	0	0	0
T20	5281	0	0	0
T21	8422	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	7	0	0
T144	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T40
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	213575868	7369	0	0
CgEnOn_A	213575868	5110	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213575868	7369	0	0
T1	646764	67	0	0
T2	466450	16	0	0
T3	26906	1	0	0
T4	47065	17	0	0
T5	16129	1	0	0
T11	61625	1	0	0
T18	1467	1	0	0
T19	16851	1	0	0
T20	2640	1	0	0
T21	4212	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213575868	5110	0	0
T1	646764	61	0	0
T2	466450	4	0	0
T3	26906	0	0	0
T4	47065	0	0	0
T11	61625	0	0	0
T12	69158	0	0	0
T15	0	2	0	0
T18	1467	0	0	0
T19	16851	0	0	0
T20	2640	0	0	0
T21	4212	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	8	0	0
T144	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445361918	3925	0	0
CgEnOn_A	445361918	3919	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	3925	0	0
T1	134740	40	0	0
T2	983755	4	0	0
T3	56053	0	0	0
T4	98051	0	0	0
T11	128385	0	0	0
T12	144076	0	0	0
T18	3056	3	0	0
T19	35106	0	0	0
T20	5501	6	0	0
T21	8774	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T105	0	6	0	0
T106	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	3919	0	0
T1	134740	40	0	0
T2	983755	4	0	0
T3	56053	0	0	0
T4	98051	0	0	0
T11	128385	0	0	0
T12	144076	0	0	0
T18	3056	3	0	0
T19	35106	0	0	0
T20	5501	6	0	0
T21	8774	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T105	0	6	0	0
T106	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445361918	3930	0	0
CgEnOn_A	445361918	3925	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	3930	0	0
T1	134740	39	0	0
T2	983755	4	0	0
T3	56053	0	0	0
T4	98051	0	0	0
T11	128385	0	0	0
T12	144076	0	0	0
T18	3056	4	0	0
T19	35106	0	0	0
T20	5501	6	0	0
T21	8774	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T105	0	5	0	0
T106	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	3925	0	0
T1	134740	39	0	0
T2	983755	4	0	0
T3	56053	0	0	0
T4	98051	0	0	0
T11	128385	0	0	0
T12	144076	0	0	0
T18	3056	4	0	0
T19	35106	0	0	0
T20	5501	6	0	0
T21	8774	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T105	0	5	0	0
T106	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445361918	3869	0	0
CgEnOn_A	445361918	3864	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	3869	0	0
T1	134740	37	0	0
T2	983755	4	0	0
T3	56053	0	0	0
T4	98051	0	0	0
T11	128385	0	0	0
T12	144076	0	0	0
T18	3056	6	0	0
T19	35106	0	0	0
T20	5501	5	0	0
T21	8774	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T105	0	5	0	0
T106	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	3864	0	0
T1	134740	37	0	0
T2	983755	4	0	0
T3	56053	0	0	0
T4	98051	0	0	0
T11	128385	0	0	0
T12	144076	0	0	0
T18	3056	6	0	0
T19	35106	0	0	0
T20	5501	5	0	0
T21	8774	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T105	0	5	0	0
T106	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445361918	3909	0	0
CgEnOn_A	445361918	3904	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	3909	0	0
T1	134740	46	0	0
T2	983755	4	0	0
T3	56053	0	0	0
T4	98051	0	0	0
T11	128385	0	0	0
T12	144076	0	0	0
T18	3056	5	0	0
T19	35106	0	0	0
T20	5501	6	0	0
T21	8774	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T105	0	4	0	0
T106	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445361918	3904	0	0
T1	134740	46	0	0
T2	983755	4	0	0
T3	56053	0	0	0
T4	98051	0	0	0
T11	128385	0	0	0
T12	144076	0	0	0
T18	3056	5	0	0
T19	35106	0	0	0
T20	5501	6	0	0
T21	8774	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T105	0	4	0	0
T106	0	1	0	0