Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T21
0	1	Covered	T1,T143,T144
1	0	Covered	T1,T5,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T37,T38,T39
1	1	Covered	T1,T5,T2

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	942363941	13405	0	0
GateOpen_A	942363941	13403	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942363941	13405	0	0
T1	1699986	171	0	0
T2	2038131	16	0	0
T3	121036	0	0	0
T4	178951	0	0	0
T11	277278	0	0	0
T12	311139	0	0	0
T15	0	1	0	0
T18	6512	0	0	0
T19	75738	0	0	0
T20	11834	0	0	0
T21	18883	4	0	0
T37	0	5	0	0
T38	0	8	0	0
T39	0	3	0	0
T106	0	4	0	0
T107	0	4	0	0
T143	0	19	0	0
T144	0	34	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942363941	13403	0	0
T1	1699986	171	0	0
T2	2038131	16	0	0
T3	121036	0	0	0
T4	178951	0	0	0
T11	277278	0	0	0
T12	311139	0	0	0
T15	0	1	0	0
T18	6512	0	0	0
T19	75738	0	0	0
T20	11834	0	0	0
T21	18883	4	0	0
T37	0	5	0	0
T38	0	8	0	0
T39	0	3	0	0
T106	0	4	0	0
T107	0	4	0	0
T143	0	19	0	0
T144	0	34	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T21
0	1	Covered	T1,T143,T144
1	0	Covered	T1,T5,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T37,T38,T39
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	103908898	3257	0	0
GateOpen_A	103908898	3255	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103908898	3257	0	0
T1	309494	36	0	0
T2	224461	4	0	0
T3	13440	0	0	0
T4	12588	0	0	0
T11	30802	0	0	0
T12	34558	0	0	0
T18	704	0	0	0
T19	8395	0	0	0
T20	1304	0	0	0
T21	2083	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	6	0	0
T144	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103908898	3255	0	0
T1	309494	36	0	0
T2	224461	4	0	0
T3	13440	0	0	0
T4	12588	0	0	0
T11	30802	0	0	0
T12	34558	0	0	0
T18	704	0	0	0
T19	8395	0	0	0
T20	1304	0	0	0
T21	2083	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	6	0	0
T144	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T21
0	1	Covered	T1,T143,T144
1	0	Covered	T1,T5,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T37,T38,T39
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	207818643	3372	0	0
GateOpen_A	207818643	3372	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207818643	3372	0	0
T1	618992	47	0	0
T2	448922	4	0	0
T3	26879	0	0	0
T4	25172	0	0	0
T11	61604	0	0	0
T12	69115	0	0	0
T18	1407	0	0	0
T19	16790	0	0	0
T20	2608	0	0	0
T21	4165	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	4	0	0
T144	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207818643	3372	0	0
T1	618992	47	0	0
T2	448922	4	0	0
T3	26879	0	0	0
T4	25172	0	0	0
T11	61604	0	0	0
T12	69115	0	0	0
T18	1407	0	0	0
T19	16790	0	0	0
T20	2608	0	0	0
T21	4165	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	4	0	0
T144	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T21
0	1	Covered	T1,T143,T144
1	0	Covered	T1,T5,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T37,T38,T39
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	417060115	3422	0	0
GateOpen_A	417060115	3422	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417060115	3422	0	0
T1	124735	46	0	0
T2	898297	4	0	0
T3	53811	0	0	0
T4	94126	0	0	0
T11	123246	0	0	0
T12	138308	0	0	0
T18	2934	0	0	0
T19	33701	0	0	0
T20	5281	0	0	0
T21	8423	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	5	0	0
T144	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417060115	3422	0	0
T1	124735	46	0	0
T2	898297	4	0	0
T3	53811	0	0	0
T4	94126	0	0	0
T11	123246	0	0	0
T12	138308	0	0	0
T18	2934	0	0	0
T19	33701	0	0	0
T20	5281	0	0	0
T21	8423	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	5	0	0
T144	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T21
0	1	Covered	T1,T143,T144
1	0	Covered	T1,T5,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T37,T38,T40
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	213576285	3354	0	0
GateOpen_A	213576285	3354	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213576285	3354	0	0
T1	646765	42	0	0
T2	466451	4	0	0
T3	26906	0	0	0
T4	47065	0	0	0
T11	61626	0	0	0
T12	69158	0	0	0
T15	0	1	0	0
T18	1467	0	0	0
T19	16852	0	0	0
T20	2641	0	0	0
T21	4212	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	4	0	0
T144	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213576285	3354	0	0
T1	646765	42	0	0
T2	466451	4	0	0
T3	26906	0	0	0
T4	47065	0	0	0
T11	61626	0	0	0
T12	69158	0	0	0
T15	0	1	0	0
T18	1467	0	0	0
T19	16852	0	0	0
T20	2641	0	0	0
T21	4212	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T106	0	1	0	0
T107	0	1	0	0
T143	0	4	0	0
T144	0	8	0	0