Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	639831	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3924878

1

T5

30

T6

13

T7

109

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1120851	1			T5	68		T6	29		T7	52
values[0x0]	1583008	1			T5	21		T6	12		T7	30
values[0x1]	1860850	1			T5	21		T6	9		T7	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	344372	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4220337

1

T5

55

T6

23

T7

115

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17927	1			T34	2		T35	4		T36	2
valid_sources[0x01]	17774	1			T34	5		T35	3		T36	1
valid_sources[0x02]	17822	1			T34	4		T35	3		T36	1
valid_sources[0x03]	18507	1			T33	1		T34	2		T48	1
valid_sources[0x04]	18299	1			T6	3		T35	2		T36	1
valid_sources[0x05]	18983	1			T34	2		T35	1		T36	4
valid_sources[0x06]	18640	1			T33	1		T35	4		T36	4
valid_sources[0x07]	17601	1			T34	4		T35	2		T36	1
valid_sources[0x08]	17112	1			T33	1		T35	2		T37	1
valid_sources[0x09]	19218	1			T34	2		T35	2		T36	1
valid_sources[0x0a]	17846	1			T33	2		T34	1		T36	1
valid_sources[0x0b]	18421	1			T33	1		T34	3		T35	2
valid_sources[0x0c]	17863	1			T33	2		T34	3		T35	1
valid_sources[0x0d]	16121	1			T34	2		T35	2		T36	3
valid_sources[0x0e]	16812	1			T34	1		T35	2		T66	2
valid_sources[0x0f]	17499	1			T34	2		T36	1		T37	2
valid_sources[0x10]	19917	1			T33	1		T34	3		T35	1
valid_sources[0x11]	18763	1			T33	1		T34	1		T35	3
valid_sources[0x12]	17086	1			T33	1		T34	6		T36	2
valid_sources[0x13]	17883	1			T34	1		T35	2		T36	1
valid_sources[0x14]	18192	1			T6	18		T33	1		T34	1
valid_sources[0x15]	17877	1			T33	1		T34	1		T35	6
valid_sources[0x16]	19078	1			T33	2		T34	3		T35	1
valid_sources[0x17]	17895	1			T33	1		T34	1		T35	3
valid_sources[0x18]	18267	1			T5	2		T34	5		T35	4
valid_sources[0x19]	17053	1			T33	3		T34	3		T35	2
valid_sources[0x1a]	16897	1			T33	2		T34	3		T35	4
valid_sources[0x1b]	17420	1			T34	2		T35	4		T36	1
valid_sources[0x1c]	16896	1			T34	1		T36	3		T37	1
valid_sources[0x1d]	17729	1			T33	2		T35	1		T36	2
valid_sources[0x1e]	17667	1			T33	1		T34	2		T35	3
valid_sources[0x1f]	17573	1			T34	1		T36	1		T37	1
valid_sources[0x20]	18774	1			T33	1		T34	3		T38	1
valid_sources[0x21]	16239	1			T5	23		T34	2		T35	7
valid_sources[0x22]	17868	1			T33	2		T34	2		T35	2
valid_sources[0x23]	18304	1			T33	2		T34	3		T35	2
valid_sources[0x24]	18340	1			T34	9		T35	4		T36	1
valid_sources[0x25]	17738	1			T33	1		T34	2		T35	5
valid_sources[0x26]	17305	1			T33	1		T34	1		T35	4
valid_sources[0x27]	16818	1			T34	2		T35	1		T38	2
valid_sources[0x28]	18005	1			T33	1		T34	3		T68	23
valid_sources[0x29]	16214	1			T6	4		T34	1		T35	2
valid_sources[0x2a]	15778	1			T33	3		T34	3		T36	1
valid_sources[0x2b]	18813	1			T34	1		T35	2		T36	1
valid_sources[0x2c]	17238	1			T33	1		T34	5		T35	1
valid_sources[0x2d]	17876	1			T34	3		T35	3		T38	2
valid_sources[0x2e]	17306	1			T33	1		T35	1		T36	4
valid_sources[0x2f]	18231	1			T34	3		T35	1		T36	2
valid_sources[0x30]	18057	1			T33	1		T35	1		T36	1
valid_sources[0x31]	17255	1			T33	1		T35	4		T65	3
valid_sources[0x32]	18772	1			T34	3		T35	1		T37	2
valid_sources[0x33]	18591	1			T34	3		T35	2		T38	1
valid_sources[0x34]	18042	1			T34	1		T36	1		T70	1
valid_sources[0x35]	17859	1			T33	1		T34	1		T38	2
valid_sources[0x36]	18102	1			T34	4		T35	1		T36	1
valid_sources[0x37]	19658	1			T33	2		T34	1		T35	3
valid_sources[0x38]	15904	1			T34	1		T35	1		T38	1
valid_sources[0x39]	18796	1			T33	1		T34	1		T36	1
valid_sources[0x3a]	17410	1			T33	1		T34	2		T35	1
valid_sources[0x3b]	18379	1			T33	1		T34	3		T35	2
valid_sources[0x3c]	18221	1			T33	2		T34	1		T35	7
valid_sources[0x3d]	19238	1			T33	1		T34	2		T35	3
valid_sources[0x3e]	18210	1			T7	53		T34	2		T35	1
valid_sources[0x3f]	20014	1			T34	2		T35	1		T48	1
valid_sources[0x40]	17839	1			T33	3		T34	1		T35	7
valid_sources[0x41]	17127	1			T34	1		T35	3		T36	1
valid_sources[0x42]	18106	1			T34	1		T35	3		T70	12
valid_sources[0x43]	17565	1			T33	1		T34	2		T35	2
valid_sources[0x44]	18449	1			T33	1		T34	5		T35	2
valid_sources[0x45]	16947	1			T35	2		T36	1		T38	1
valid_sources[0x46]	18085	1			T34	8		T35	1		T36	2
valid_sources[0x47]	17584	1			T33	1		T34	1		T35	3
valid_sources[0x48]	16987	1			T37	1		T70	4		T66	4
valid_sources[0x49]	17560	1			T34	1		T35	3		T38	1
valid_sources[0x4a]	17392	1			T34	2		T35	1		T37	2
valid_sources[0x4b]	17942	1			T33	1		T34	4		T35	3
valid_sources[0x4c]	16628	1			T33	2		T34	1		T35	2
valid_sources[0x4d]	17312	1			T7	64		T34	1		T35	2
valid_sources[0x4e]	17031	1			T33	1		T34	1		T35	1
valid_sources[0x4f]	17977	1			T35	1		T36	1		T75	12
valid_sources[0x50]	18130	1			T34	3		T38	2		T70	2
valid_sources[0x51]	17898	1			T33	1		T34	1		T35	3
valid_sources[0x52]	18212	1			T33	2		T34	1		T35	3
valid_sources[0x53]	17543	1			T33	2		T34	3		T35	3
valid_sources[0x54]	16820	1			T33	1		T34	3		T35	3
valid_sources[0x55]	17192	1			T33	2		T34	1		T38	2
valid_sources[0x56]	18148	1			T33	1		T35	1		T68	11
valid_sources[0x57]	18028	1			T34	2		T35	3		T36	2
valid_sources[0x58]	17098	1			T5	3		T33	1		T35	1
valid_sources[0x59]	17402	1			T34	4		T35	4		T68	7
valid_sources[0x5a]	17639	1			T5	4		T33	1		T34	4
valid_sources[0x5b]	18210	1			T33	1		T34	1		T35	4
valid_sources[0x5c]	18990	1			T33	1		T35	1		T38	1
valid_sources[0x5d]	17204	1			T34	5		T35	2		T38	1
valid_sources[0x5e]	19222	1			T33	1		T34	2		T35	1
valid_sources[0x5f]	17674	1			T33	2		T34	5		T35	1
valid_sources[0x60]	18324	1			T33	1		T34	1		T35	2
valid_sources[0x61]	17395	1			T33	4		T34	1		T35	1
valid_sources[0x62]	17494	1			T34	5		T35	5		T36	1
valid_sources[0x63]	19157	1			T34	1		T35	7		T36	1
valid_sources[0x64]	18183	1			T33	1		T34	3		T35	6
valid_sources[0x65]	16200	1			T33	1		T34	1		T35	1
valid_sources[0x66]	17096	1			T33	1		T34	4		T35	1
valid_sources[0x67]	17140	1			T70	1		T48	3		T77	1
valid_sources[0x68]	18222	1			T34	4		T35	2		T37	1
valid_sources[0x69]	17631	1			T34	3		T38	1		T70	17
valid_sources[0x6a]	17837	1			T35	4		T36	2		T38	2
valid_sources[0x6b]	16894	1			T33	1		T34	4		T36	3
valid_sources[0x6c]	16590	1			T33	1		T35	2		T36	3
valid_sources[0x6d]	17041	1			T34	4		T38	1		T68	17
valid_sources[0x6e]	18010	1			T34	4		T70	6		T66	1
valid_sources[0x6f]	18202	1			T5	14		T33	2		T34	3
valid_sources[0x70]	16664	1			T33	1		T34	3		T35	1
valid_sources[0x71]	17547	1			T33	1		T34	3		T35	6
valid_sources[0x72]	18673	1			T34	3		T35	4		T36	1
valid_sources[0x73]	18332	1			T35	4		T36	1		T38	3
valid_sources[0x74]	17957	1			T34	1		T35	2		T36	1
valid_sources[0x75]	17114	1			T33	1		T34	5		T35	1
valid_sources[0x76]	19554	1			T34	1		T35	1		T36	1
valid_sources[0x77]	16609	1			T34	1		T37	1		T38	1
valid_sources[0x78]	17035	1			T33	1		T34	2		T35	1
valid_sources[0x79]	17330	1			T33	2		T35	5		T36	1
valid_sources[0x7a]	18477	1			T34	2		T35	2		T38	1
valid_sources[0x7b]	17764	1			T33	1		T35	1		T36	1
valid_sources[0x7c]	18263	1			T34	1		T35	2		T36	3
valid_sources[0x7d]	18208	1			T33	2		T35	3		T37	2
valid_sources[0x7e]	16899	1			T33	1		T34	2		T37	2
valid_sources[0x7f]	17207	1			T34	2		T35	2		T36	2
valid_sources[0x80]	17772	1			T33	2		T34	1		T35	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

990889

1

T5

8

T6

4

T7

35

values[0x0]

all_enables

biggest_size

1490740

1

T5

13

T6

5

T7

30

values[0x1]

all_enables

biggest_size

1443249

1

T5

9

T6

4

T7

44