Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	827600680	73841	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827600680	73841	0	0
T1	72275	50	0	0
T2	1651205	615	0	0
T3	653535	185	0	0
T4	68950	0	0	0
T9	2341485	1414	0	0
T10	0	1338	0	0
T11	0	128	0	0
T12	0	601	0	0
T13	0	1671	0	0
T14	0	258	0	0
T15	0	513	0	0
T16	9350	0	0	0
T17	4935	0	0	0
T18	11320	0	0	0
T19	214920	0	0	0
T20	5480	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165520136	10912	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	10912	0	0
T1	14455	8	0	0
T2	330241	98	0	0
T3	130707	27	0	0
T4	13790	0	0	0
T9	468297	209	0	0
T10	0	177	0	0
T11	0	20	0	0
T12	0	75	0	0
T13	0	221	0	0
T14	0	42	0	0
T15	0	86	0	0
T16	1870	0	0	0
T17	987	0	0	0
T18	2264	0	0	0
T19	42984	0	0	0
T20	1096	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165520136	14863	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	14863	0	0
T1	14455	10	0	0
T2	330241	126	0	0
T3	130707	38	0	0
T4	13790	0	0	0
T9	468297	287	0	0
T10	0	270	0	0
T11	0	26	0	0
T12	0	121	0	0
T13	0	339	0	0
T14	0	52	0	0
T15	0	104	0	0
T16	1870	0	0	0
T17	987	0	0	0
T18	2264	0	0	0
T19	42984	0	0	0
T20	1096	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165520136	22464	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	22464	0	0
T1	14455	14	0	0
T2	330241	172	0	0
T3	130707	57	0	0
T4	13790	0	0	0
T9	468297	462	0	0
T10	0	444	0	0
T11	0	36	0	0
T12	0	197	0	0
T13	0	558	0	0
T14	0	70	0	0
T15	0	133	0	0
T16	1870	0	0	0
T17	987	0	0	0
T18	2264	0	0	0
T19	42984	0	0	0
T20	1096	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165520136	10618	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	10618	0	0
T1	14455	8	0	0
T2	330241	95	0	0
T3	130707	26	0	0
T4	13790	0	0	0
T9	468297	178	0	0
T10	0	176	0	0
T11	0	20	0	0
T12	0	86	0	0
T13	0	214	0	0
T14	0	42	0	0
T15	0	86	0	0
T16	1870	0	0	0
T17	987	0	0	0
T18	2264	0	0	0
T19	42984	0	0	0
T20	1096	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165520136	14984	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	14984	0	0
T1	14455	10	0	0
T2	330241	124	0	0
T3	130707	37	0	0
T4	13790	0	0	0
T9	468297	278	0	0
T10	0	271	0	0
T11	0	26	0	0
T12	0	122	0	0
T13	0	339	0	0
T14	0	52	0	0
T15	0	104	0	0
T16	1870	0	0	0
T17	987	0	0	0
T18	2264	0	0	0
T19	42984	0	0	0
T20	1096	0	0	0