Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_step_down_req_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_io_div2_div_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_div4_div_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_io_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_main_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_usb_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_io_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_usb_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_io_step_down_req_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_div_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_div4_div_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_main_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div2_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div4_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div2_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div4_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_main_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_usb_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_io_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_step_down_req_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_usb_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	6	6

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Cond Coverage for Module : prim_mubi4_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

---

Branch Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	21924	21924	0	0
OutputsKnown_A	2147483647	2147483647	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	993120816	977620932	0	14094
gen_flops.gen_stable_chks.OutputDelay_A	2147483647	2147483647	0	16443
gen_flops.gen_stable_chks.OutputIfUnstable_A	2147483647	189356	0	0
gen_no_flops.OutputDelay_A	2147483647	2147483647	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21924	21924	0	0
T1	28	28	0	0
T2	28	28	0	0
T4	28	28	0	0
T16	28	28	0	0
T17	28	28	0	0
T18	28	28	0	0
T21	28	28	0	0
T22	28	28	0	0
T23	28	28	0	0
T24	28	28	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	932327	930822	0	0
T2	7629940	7625055	0	0
T4	431827	430740	0	0
T16	49800	46052	0	0
T17	86764	84194	0	0
T18	88073	86425	0	0
T21	41538	37490	0	0
T22	125683	124945	0	0
T23	48600	43160	0	0
T24	44365	43221	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	993120816	977620932	0	14094
T1	86730	86550	0	18
T2	1981446	1979856	0	18
T4	82740	82494	0	18
T16	11220	10308	0	18
T17	5922	5718	0	18
T18	13584	13278	0	18
T21	9528	8496	0	18
T22	11604	11508	0	18
T23	11058	9708	0	18
T24	9012	8742	0	18

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	16443
T1	327654	327028	0	21
T2	1312199	1311148	0	21
T4	125301	124932	0	21
T16	13402	12314	0	21
T17	31904	30770	0	21
T18	27438	26836	0	21
T21	11053	9856	0	21
T22	43855	43536	0	21
T23	13010	11424	0	21
T24	12562	12184	0	21

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	189356	0	0
T1	327654	4	0	0
T2	1312199	3601	0	0
T3	0	234	0	0
T4	125301	4	0	0
T9	0	568	0	0
T16	13402	130	0	0
T17	31904	53	0	0
T18	27438	155	0	0
T20	0	11	0	0
T21	11053	102	0	0
T22	43855	169	0	0
T23	13010	123	0	0
T24	12562	20	0	0
T28	0	58	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	517943	517205	0	0
T2	4336295	4334035	0	0
T4	223786	223275	0	0
T16	25178	23391	0	0
T17	48938	47667	0	0
T18	47051	46272	0	0
T21	20957	19099	0	0
T22	70224	69862	0	0
T23	24532	21989	0	0
T24	22791	22256	0	0

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	494351189	490350029	0	0
gen_flops.gen_stable_chks.OutputDelay_A	494351189	490343456	0	2349
gen_flops.gen_stable_chks.OutputIfUnstable_A	494351189	25533	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351189	490350029	0	0
T1	57820	57713	0	0
T2	125253	125152	0	0
T4	18913	18861	0	0
T16	1870	1721	0	0
T17	5518	5315	0	0
T18	4434	4341	0	0
T21	1525	1363	0	0
T22	7739	7687	0	0
T23	1804	1587	0	0
T24	1850	1797	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351189	490343456	0	2349
T1	57820	57710	0	3
T2	125253	125152	0	3
T4	18913	18858	0	3
T16	1870	1718	0	3
T17	5518	5312	0	3
T18	4434	4338	0	3
T21	1525	1360	0	3
T22	7739	7684	0	3
T23	1804	1584	0	3
T24	1850	1794	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351189	25533	0	0
T1	57820	0	0	0
T2	125253	409	0	0
T3	0	100	0	0
T4	18913	0	0	0
T9	0	230	0	0
T16	1870	38	0	0
T17	5518	0	0	0
T18	4434	38	0	0
T20	0	5	0	0
T21	1525	19	0	0
T22	7739	37	0	0
T23	1804	50	0	0
T24	1850	0	0	0
T28	0	24	0	0

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_no_flops.OutputDelay_A	165520136	162943543	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_no_flops.OutputDelay_A	165520136	162943543	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_flops.gen_stable_chks.OutputDelay_A	165520136	162936822	0	2349
gen_flops.gen_stable_chks.OutputIfUnstable_A	165520136	15955	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162936822	0	2349
T1	14455	14425	0	3
T2	330241	329976	0	3
T4	13790	13749	0	3
T16	1870	1718	0	3
T17	987	953	0	3
T18	2264	2213	0	3
T21	1588	1416	0	3
T22	1934	1918	0	3
T23	1843	1618	0	3
T24	1502	1457	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	15955	0	0
T1	14455	0	0	0
T2	330241	275	0	0
T3	0	62	0	0
T4	13790	0	0	0
T9	0	163	0	0
T16	1870	4	0	0
T17	987	0	0	0
T18	2264	31	0	0
T20	0	3	0	0
T21	1588	31	0	0
T22	1934	52	0	0
T23	1843	16	0	0
T24	1502	0	0	0
T28	0	17	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_flops.gen_stable_chks.OutputDelay_A	165520136	162936822	0	2349
gen_flops.gen_stable_chks.OutputIfUnstable_A	165520136	18156	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162936822	0	2349
T1	14455	14425	0	3
T2	330241	329976	0	3
T4	13790	13749	0	3
T16	1870	1718	0	3
T17	987	953	0	3
T18	2264	2213	0	3
T21	1588	1416	0	3
T22	1934	1918	0	3
T23	1843	1618	0	3
T24	1502	1457	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	18156	0	0
T1	14455	0	0	0
T2	330241	319	0	0
T3	0	72	0	0
T4	13790	0	0	0
T9	0	175	0	0
T16	1870	36	0	0
T17	987	0	0	0
T18	2264	27	0	0
T20	0	3	0	0
T21	1588	26	0	0
T22	1934	44	0	0
T23	1843	15	0	0
T24	1502	0	0	0
T28	0	17	0	0

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	524810617	522699787	0	0
gen_no_flops.OutputDelay_A	524810617	522699787	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	522699787	0	0
T1	60231	60177	0	0
T2	131616	131577	0	0
T4	19702	19676	0	0
T16	1948	1836	0	0
T17	6103	6005	0	0
T18	4619	4578	0	0
T21	1588	1519	0	0
T22	8062	8035	0	0
T23	1880	1754	0	0
T24	1927	1901	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	522699787	0	0
T1	60231	60177	0	0
T2	131616	131577	0	0
T4	19702	19676	0	0
T16	1948	1836	0	0
T17	6103	6005	0	0
T18	4619	4578	0	0
T21	1588	1519	0	0
T22	8062	8035	0	0
T23	1880	1754	0	0
T24	1927	1901	0	0

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	494351189	492353009	0	0
gen_no_flops.OutputDelay_A	494351189	492353009	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351189	492353009	0	0
T1	57820	57768	0	0
T2	125253	125216	0	0
T4	18913	18888	0	0
T16	1870	1762	0	0
T17	5518	5425	0	0
T18	4434	4395	0	0
T21	1525	1459	0	0
T22	7739	7714	0	0
T23	1804	1683	0	0
T24	1850	1825	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351189	492353009	0	0
T1	57820	57768	0	0
T2	125253	125216	0	0
T4	18913	18888	0	0
T16	1870	1762	0	0
T17	5518	5425	0	0
T18	4434	4395	0	0
T21	1525	1459	0	0
T22	7739	7714	0	0
T23	1804	1683	0	0
T24	1850	1825	0	0

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	246436945	246436945	0	0
gen_no_flops.OutputDelay_A	246436945	246436945	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246436945	246436945	0	0
T1	28884	28884	0	0
T2	626498	626498	0	0
T4	9444	9444	0	0
T16	943	943	0	0
T17	2713	2713	0	0
T18	2482	2482	0	0
T21	802	802	0	0
T22	4469	4469	0	0
T23	913	913	0	0
T24	913	913	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246436945	246436945	0	0
T1	28884	28884	0	0
T2	626498	626498	0	0
T4	9444	9444	0	0
T16	943	943	0	0
T17	2713	2713	0	0
T18	2482	2482	0	0
T21	802	802	0	0
T22	4469	4469	0	0
T23	913	913	0	0
T24	913	913	0	0

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	123217885	123217885	0	0
gen_no_flops.OutputDelay_A	123217885	123217885	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123217885	123217885	0	0
T1	14442	14442	0	0
T2	313248	313248	0	0
T4	4722	4722	0	0
T16	470	470	0	0
T17	1356	1356	0	0
T18	1239	1239	0	0
T21	400	400	0	0
T22	2233	2233	0	0
T23	455	455	0	0
T24	456	456	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123217885	123217885	0	0
T1	14442	14442	0	0
T2	313248	313248	0	0
T4	4722	4722	0	0
T16	470	470	0	0
T17	1356	1356	0	0
T18	1239	1239	0	0
T21	400	400	0	0
T22	2233	2233	0	0
T23	455	455	0	0
T24	456	456	0	0

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	252037411	251027499	0	0
gen_no_flops.OutputDelay_A	252037411	251027499	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252037411	251027499	0	0
T1	28912	28886	0	0
T2	631770	631584	0	0
T4	9457	9445	0	0
T16	935	882	0	0
T17	2914	2868	0	0
T18	2217	2198	0	0
T21	762	729	0	0
T22	3869	3857	0	0
T23	902	842	0	0
T24	925	913	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252037411	251027499	0	0
T1	28912	28886	0	0
T2	631770	631584	0	0
T4	9457	9445	0	0
T16	935	882	0	0
T17	2914	2868	0	0
T18	2217	2198	0	0
T21	762	729	0	0
T22	3869	3857	0	0
T23	902	842	0	0
T24	925	913	0	0

Line Coverage for Instance : tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	6	6

---

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165520136	162936822	0	2349

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162936822	0	2349
T1	14455	14425	0	3
T2	330241	329976	0	3
T4	13790	13749	0	3
T16	1870	1718	0	3
T17	987	953	0	3
T18	2264	2213	0	3
T21	1588	1416	0	3
T22	1934	1918	0	3
T23	1843	1618	0	3
T24	1502	1457	0	3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165520136	162936822	0	2349

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162936822	0	2349
T1	14455	14425	0	3
T2	330241	329976	0	3
T4	13790	13749	0	3
T16	1870	1718	0	3
T17	987	953	0	3
T18	2264	2213	0	3
T21	1588	1416	0	3
T22	1934	1918	0	3
T23	1843	1618	0	3
T24	1502	1457	0	3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165520136	162936822	0	2349

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162936822	0	2349
T1	14455	14425	0	3
T2	330241	329976	0	3
T4	13790	13749	0	3
T16	1870	1718	0	3
T17	987	953	0	3
T18	2264	2213	0	3
T21	1588	1416	0	3
T22	1934	1918	0	3
T23	1843	1618	0	3
T24	1502	1457	0	3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165520136	162936822	0	2349

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162936822	0	2349
T1	14455	14425	0	3
T2	330241	329976	0	3
T4	13790	13749	0	3
T16	1870	1718	0	3
T17	987	953	0	3
T18	2264	2213	0	3
T21	1588	1416	0	3
T22	1934	1918	0	3
T23	1843	1618	0	3
T24	1502	1457	0	3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165520136	162936822	0	2349

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162936822	0	2349
T1	14455	14425	0	3
T2	330241	329976	0	3
T4	13790	13749	0	3
T16	1870	1718	0	3
T17	987	953	0	3
T18	2264	2213	0	3
T21	1588	1416	0	3
T22	1934	1918	0	3
T23	1843	1618	0	3
T24	1502	1457	0	3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165520136	162936822	0	2349

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162936822	0	2349
T1	14455	14425	0	3
T2	330241	329976	0	3
T4	13790	13749	0	3
T16	1870	1718	0	3
T17	987	953	0	3
T18	2264	2213	0	3
T21	1588	1416	0	3
T22	1934	1918	0	3
T23	1843	1618	0	3
T24	1502	1457	0	3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_no_flops.OutputDelay_A	165520136	162943543	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_no_flops.OutputDelay_A	165520136	162943543	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_no_flops.OutputDelay_A	165520136	162943543	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	165520136	162943543	0	0
gen_no_flops.OutputDelay_A	165520136	162943543	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162943543	0	0
T1	14455	14428	0	0
T2	330241	329978	0	0
T4	13790	13752	0	0
T16	1870	1721	0	0
T17	987	956	0	0
T18	2264	2216	0	0
T21	1588	1419	0	0
T22	1934	1921	0	0
T23	1843	1621	0	0
T24	1502	1460	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	524810617	520607199	0	0
gen_flops.gen_stable_chks.OutputDelay_A	524810617	520600585	0	2349
gen_flops.gen_stable_chks.OutputIfUnstable_A	524810617	32475	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520600585	0	2349
T1	60231	60117	0	3
T2	131616	131511	0	3
T4	19702	19644	0	3
T16	1948	1790	0	3
T17	6103	5888	0	3
T18	4619	4518	0	3
T21	1588	1416	0	3
T22	8062	8004	0	3
T23	1880	1651	0	3
T24	1927	1869	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	32475	0	0
T1	60231	1	0	0
T2	131616	650	0	0
T4	19702	1	0	0
T16	1948	16	0	0
T17	6103	11	0	0
T18	4619	14	0	0
T21	1588	5	0	0
T22	8062	14	0	0
T23	1880	13	0	0
T24	1927	5	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	524810617	520607199	0	0
gen_no_flops.OutputDelay_A	524810617	520607199	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	524810617	520607199	0	0
gen_flops.gen_stable_chks.OutputDelay_A	524810617	520600585	0	2349
gen_flops.gen_stable_chks.OutputIfUnstable_A	524810617	32142	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520600585	0	2349
T1	60231	60117	0	3
T2	131616	131511	0	3
T4	19702	19644	0	3
T16	1948	1790	0	3
T17	6103	5888	0	3
T18	4619	4518	0	3
T21	1588	1416	0	3
T22	8062	8004	0	3
T23	1880	1651	0	3
T24	1927	1869	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	32142	0	0
T1	60231	1	0	0
T2	131616	657	0	0
T4	19702	1	0	0
T16	1948	7	0	0
T17	6103	10	0	0
T18	4619	18	0	0
T21	1588	7	0	0
T22	8062	6	0	0
T23	1880	13	0	0
T24	1927	5	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	524810617	520607199	0	0
gen_no_flops.OutputDelay_A	524810617	520607199	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	524810617	520607199	0	0
gen_flops.gen_stable_chks.OutputDelay_A	524810617	520600585	0	2349
gen_flops.gen_stable_chks.OutputIfUnstable_A	524810617	32536	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520600585	0	2349
T1	60231	60117	0	3
T2	131616	131511	0	3
T4	19702	19644	0	3
T16	1948	1790	0	3
T17	6103	5888	0	3
T18	4619	4518	0	3
T21	1588	1416	0	3
T22	8062	8004	0	3
T23	1880	1651	0	3
T24	1927	1869	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	32536	0	0
T1	60231	1	0	0
T2	131616	641	0	0
T4	19702	1	0	0
T16	1948	13	0	0
T17	6103	14	0	0
T18	4619	16	0	0
T21	1588	5	0	0
T22	8062	8	0	0
T23	1880	7	0	0
T24	1927	5	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	524810617	520607199	0	0
gen_no_flops.OutputDelay_A	524810617	520607199	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	524810617	520607199	0	0
gen_flops.gen_stable_chks.OutputDelay_A	524810617	520600585	0	2349
gen_flops.gen_stable_chks.OutputIfUnstable_A	524810617	32559	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520600585	0	2349
T1	60231	60117	0	3
T2	131616	131511	0	3
T4	19702	19644	0	3
T16	1948	1790	0	3
T17	6103	5888	0	3
T18	4619	4518	0	3
T21	1588	1416	0	3
T22	8062	8004	0	3
T23	1880	1651	0	3
T24	1927	1869	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	32559	0	0
T1	60231	1	0	0
T2	131616	650	0	0
T4	19702	1	0	0
T16	1948	16	0	0
T17	6103	18	0	0
T18	4619	11	0	0
T21	1588	9	0	0
T22	8062	8	0	0
T23	1880	9	0	0
T24	1927	5	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	783	783	0	0
OutputsKnown_A	524810617	520607199	0	0
gen_no_flops.OutputDelay_A	524810617	520607199	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783	783	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	520607199	0	0
T1	60231	60120	0	0
T2	131616	131511	0	0
T4	19702	19647	0	0
T16	1948	1793	0	0
T17	6103	5891	0	0
T18	4619	4521	0	0
T21	1588	1419	0	0
T22	8062	8007	0	0
T23	1880	1654	0	0
T24	1927	1872	0	0