Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Unreachable
1	0	Covered	T2,T3,T9

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	165520136	162819834	0	0
AllClkBypReqTrue_A	165520136	121518	0	0
IoClkBypReqFalse_A	165520136	162746127	0	2349
IoClkBypReqTrue_A	165520136	190843	0	0
LcClkBypAckFalse_A	165520136	162830293	0	0
LcClkBypAckTrue_A	165520136	111059	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162819834	0	0
T1	14455	14427	0	0
T2	330241	329822	0	0
T4	13790	13751	0	0
T16	1870	1652	0	0
T17	987	955	0	0
T18	2264	2000	0	0
T21	1588	1287	0	0
T22	1934	1562	0	0
T23	1843	1490	0	0
T24	1502	1459	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	121518	0	0
T1	14455	0	0	0
T2	330241	1552	0	0
T3	0	409	0	0
T4	13790	0	0	0
T9	0	904	0	0
T16	1870	68	0	0
T17	987	0	0	0
T18	2264	215	0	0
T21	1588	131	0	0
T22	1934	358	0	0
T23	1843	130	0	0
T24	1502	0	0	0
T28	0	82	0	0
T30	0	41	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162746127	0	2349
T1	14455	14425	0	3
T2	330241	329727	0	3
T4	13790	13749	0	3
T16	1870	1690	0	3
T17	987	953	0	3
T18	2264	1760	0	3
T21	1588	1280	0	3
T22	1934	1530	0	3
T23	1843	1454	0	3
T24	1502	1457	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	190843	0	0
T1	14455	0	0	0
T2	330241	2494	0	0
T3	0	506	0	0
T4	13790	0	0	0
T9	0	1496	0	0
T16	1870	28	0	0
T17	987	0	0	0
T18	2264	453	0	0
T20	0	33	0	0
T21	1588	136	0	0
T22	1934	388	0	0
T23	1843	164	0	0
T24	1502	0	0	0
T28	0	264	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	162830293	0	0
T1	14455	14427	0	0
T2	330241	329814	0	0
T4	13790	13751	0	0
T16	1870	1697	0	0
T17	987	955	0	0
T18	2264	1985	0	0
T21	1588	1330	0	0
T22	1934	1731	0	0
T23	1843	1528	0	0
T24	1502	1459	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165520136	111059	0	0
T1	14455	0	0	0
T2	330241	1638	0	0
T3	0	248	0	0
T4	13790	0	0	0
T9	0	892	0	0
T16	1870	23	0	0
T17	987	0	0	0
T18	2264	230	0	0
T21	1588	88	0	0
T22	1934	189	0	0
T23	1843	92	0	0
T24	1502	0	0	0
T28	0	141	0	0
T100	0	209	0	0