Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2099244088	15796	0	0
TransStop_A	2099244088	7961	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2099244088	15796	0	0
T1	240924	0	0	0
T2	526464	353	0	0
T3	1021660	8	0	0
T4	78808	0	0	0
T9	1910500	414	0	0
T10	0	42	0	0
T12	0	51	0	0
T16	7796	0	0	0
T17	24412	0	0	0
T18	18480	0	0	0
T19	491240	0	0	0
T24	7708	4	0	0
T101	0	33	0	0
T102	0	4	0	0
T103	0	27	0	0
T104	0	37	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2099244088	7961	0	0
T1	240924	0	0	0
T2	526464	180	0	0
T3	1021660	2	0	0
T4	78808	0	0	0
T9	1910500	181	0	0
T10	0	19	0	0
T12	0	23	0	0
T16	7796	0	0	0
T17	24412	0	0	0
T18	18480	0	0	0
T19	491240	0	0	0
T24	7708	4	0	0
T101	0	12	0	0
T103	0	15	0	0
T104	0	18	0	0
T105	0	6	0	0
T106	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	524811022	3944	0	0
TransStop_A	524811022	2015	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524811022	3944	0	0
T1	60231	0	0	0
T2	131616	85	0	0
T3	255415	2	0	0
T4	19702	0	0	0
T9	477625	102	0	0
T10	0	10	0	0
T12	0	15	0	0
T16	1949	0	0	0
T17	6103	0	0	0
T18	4620	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T101	0	9	0	0
T102	0	1	0	0
T103	0	9	0	0
T104	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524811022	2015	0	0
T1	60231	0	0	0
T2	131616	43	0	0
T3	255415	0	0	0
T4	19702	0	0	0
T9	477625	47	0	0
T10	0	5	0	0
T12	0	6	0	0
T16	1949	0	0	0
T17	6103	0	0	0
T18	4620	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T101	0	4	0	0
T103	0	4	0	0
T104	0	5	0	0
T105	0	2	0	0
T106	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	524811022	3939	0	0
TransStop_A	524811022	1949	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524811022	3939	0	0
T1	60231	0	0	0
T2	131616	90	0	0
T3	255415	2	0	0
T4	19702	0	0	0
T9	477625	102	0	0
T10	0	12	0	0
T12	0	14	0	0
T16	1949	0	0	0
T17	6103	0	0	0
T18	4620	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T101	0	8	0	0
T102	0	1	0	0
T103	0	5	0	0
T104	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524811022	1949	0	0
T1	60231	0	0	0
T2	131616	43	0	0
T3	255415	1	0	0
T4	19702	0	0	0
T9	477625	39	0	0
T10	0	7	0	0
T12	0	6	0	0
T16	1949	0	0	0
T17	6103	0	0	0
T18	4620	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T101	0	3	0	0
T103	0	4	0	0
T104	0	3	0	0
T105	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	524811022	3899	0	0
TransStop_A	524811022	1965	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524811022	3899	0	0
T1	60231	0	0	0
T2	131616	92	0	0
T3	255415	3	0	0
T4	19702	0	0	0
T9	477625	108	0	0
T10	0	8	0	0
T12	0	11	0	0
T16	1949	0	0	0
T17	6103	0	0	0
T18	4620	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T101	0	9	0	0
T102	0	1	0	0
T103	0	5	0	0
T104	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524811022	1965	0	0
T1	60231	0	0	0
T2	131616	49	0	0
T3	255415	1	0	0
T4	19702	0	0	0
T9	477625	48	0	0
T10	0	2	0	0
T12	0	6	0	0
T16	1949	0	0	0
T17	6103	0	0	0
T18	4620	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T101	0	2	0	0
T103	0	3	0	0
T104	0	6	0	0
T105	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	524811022	4014	0	0
TransStop_A	524811022	2032	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524811022	4014	0	0
T1	60231	0	0	0
T2	131616	86	0	0
T3	255415	1	0	0
T4	19702	0	0	0
T9	477625	102	0	0
T10	0	12	0	0
T12	0	11	0	0
T16	1949	0	0	0
T17	6103	0	0	0
T18	4620	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T101	0	7	0	0
T102	0	1	0	0
T103	0	8	0	0
T104	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524811022	2032	0	0
T1	60231	0	0	0
T2	131616	45	0	0
T3	255415	0	0	0
T4	19702	0	0	0
T9	477625	47	0	0
T10	0	5	0	0
T12	0	5	0	0
T16	1949	0	0	0
T17	6103	0	0	0
T18	4620	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T101	0	3	0	0
T103	0	4	0	0
T104	0	4	0	0
T105	0	1	0	0
T106	0	1	0	0