Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	166462037	5762542	0	0
clk_enables_rd_A	166462037	50236	0	0
clk_hints_rd_A	166462037	44512	0	0
extclk_ctrl_rd_A	166462037	55101	0	0
extclk_ctrl_regwen_rd_A	166462037	43022	0	0
jitter_enable_rd_A	166462037	60550	0	0
jitter_regwen_rd_A	166462037	48518	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166462037	5762542	0	0
T7	1764	30	0	0
T33	5349	0	0	0
T34	8772	0	0	0
T35	5386	5	0	0
T36	2001	194	0	0
T37	2179	20	0	0
T38	1273	0	0	0
T39	651	0	0	0
T65	1734	0	0	0
T66	0	901	0	0
T67	0	396	0	0
T68	10244	0	0	0
T76	0	3	0	0
T77	0	223	0	0
T78	0	573	0	0
T84	0	7	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166462037	50236	0	0
T7	1764	1	0	0
T33	5349	0	0	0
T34	8772	28	0	0
T35	5386	0	0	0
T36	2001	0	0	0
T37	2179	0	0	0
T38	1273	0	0	0
T39	651	0	0	0
T65	1734	5	0	0
T67	0	34	0	0
T68	10244	0	0	0
T70	0	285	0	0
T74	0	453	0	0
T75	0	122	0	0
T77	0	7	0	0
T87	0	25	0	0
T130	0	12	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166462037	44512	0	0
T7	1764	6	0	0
T33	5349	0	0	0
T34	8772	40	0	0
T35	5386	0	0	0
T36	2001	0	0	0
T37	2179	0	0	0
T38	1273	0	0	0
T39	651	0	0	0
T65	1734	9	0	0
T67	0	26	0	0
T68	10244	0	0	0
T70	0	238	0	0
T75	0	85	0	0
T77	0	24	0	0
T86	0	27	0	0
T87	0	43	0	0
T91	0	9	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166462037	55101	0	0
T7	1764	6	0	0
T33	5349	0	0	0
T34	8772	54	0	0
T35	5386	0	0	0
T36	2001	0	0	0
T37	2179	0	0	0
T38	1273	0	0	0
T39	651	0	0	0
T65	1734	0	0	0
T67	0	16	0	0
T68	10244	0	0	0
T70	0	14	0	0
T74	0	45	0	0
T77	0	18	0	0
T87	0	49	0	0
T89	0	133	0	0
T130	0	6	0	0
T131	0	9	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166462037	43022	0	0
T7	1764	10	0	0
T33	5349	0	0	0
T34	8772	43	0	0
T35	5386	0	0	0
T36	2001	0	0	0
T37	2179	0	0	0
T38	1273	0	0	0
T39	651	0	0	0
T65	1734	0	0	0
T67	0	34	0	0
T68	10244	0	0	0
T70	0	120	0	0
T74	0	216	0	0
T75	0	48	0	0
T77	0	22	0	0
T86	0	5	0	0
T87	0	63	0	0
T130	0	8	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166462037	60550	0	0
T7	1764	9	0	0
T33	5349	0	0	0
T34	8772	26	0	0
T35	5386	0	0	0
T36	2001	0	0	0
T37	2179	0	0	0
T38	1273	0	0	0
T39	651	0	0	0
T65	1734	0	0	0
T67	0	21	0	0
T68	10244	0	0	0
T70	0	77	0	0
T74	0	203	0	0
T75	0	73	0	0
T77	0	17	0	0
T86	0	3	0	0
T87	0	41	0	0
T130	0	14	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166462037	48518	0	0
T7	1764	9	0	0
T33	5349	0	0	0
T34	8772	23	0	0
T35	5386	0	0	0
T36	2001	0	0	0
T37	2179	0	0	0
T38	1273	0	0	0
T39	651	0	0	0
T65	1734	0	0	0
T67	0	13	0	0
T68	10244	0	0	0
T70	0	110	0	0
T74	0	196	0	0
T75	0	46	0	0
T77	0	17	0	0
T87	0	15	0	0
T91	0	4	0	0
T130	0	4	0	0