Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	494351619	4092	0	0
g_div2.Div2Whole_A	494351619	4853	0	0
g_div4.Div4Stepped_A	246437338	4011	0	0
g_div4.Div4Whole_A	246437338	4610	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351619	4092	0	0
T1	57821	0	0	0
T2	125253	76	0	0
T3	0	13	0	0
T4	18913	0	0	0
T9	0	33	0	0
T16	1871	3	0	0
T17	5519	0	0	0
T18	4435	8	0	0
T21	1525	5	0	0
T22	7739	8	0	0
T23	1805	4	0	0
T24	1851	0	0	0
T28	0	3	0	0
T30	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351619	4853	0	0
T1	57821	0	0	0
T2	125253	90	0	0
T3	0	16	0	0
T4	18913	0	0	0
T9	0	44	0	0
T16	1871	10	0	0
T17	5519	0	0	0
T18	4435	9	0	0
T21	1525	5	0	0
T22	7739	9	0	0
T23	1805	4	0	0
T24	1851	0	0	0
T28	0	5	0	0
T30	0	5	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246437338	4011	0	0
T1	28885	0	0	0
T2	626498	76	0	0
T3	0	11	0	0
T4	9445	0	0	0
T9	0	30	0	0
T16	944	3	0	0
T17	2713	0	0	0
T18	2482	8	0	0
T21	802	4	0	0
T22	4470	8	0	0
T23	913	3	0	0
T24	913	0	0	0
T28	0	3	0	0
T30	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246437338	4610	0	0
T1	28885	0	0	0
T2	626498	89	0	0
T3	0	16	0	0
T4	9445	0	0	0
T9	0	39	0	0
T16	944	8	0	0
T17	2713	0	0	0
T18	2482	9	0	0
T21	802	2	0	0
T22	4470	9	0	0
T23	913	4	0	0
T24	913	0	0	0
T28	0	5	0	0
T30	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	494351619	4092	0	0
g_div2.Div2Whole_A	494351619	4853	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351619	4092	0	0
T1	57821	0	0	0
T2	125253	76	0	0
T3	0	13	0	0
T4	18913	0	0	0
T9	0	33	0	0
T16	1871	3	0	0
T17	5519	0	0	0
T18	4435	8	0	0
T21	1525	5	0	0
T22	7739	8	0	0
T23	1805	4	0	0
T24	1851	0	0	0
T28	0	3	0	0
T30	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351619	4853	0	0
T1	57821	0	0	0
T2	125253	90	0	0
T3	0	16	0	0
T4	18913	0	0	0
T9	0	44	0	0
T16	1871	10	0	0
T17	5519	0	0	0
T18	4435	9	0	0
T21	1525	5	0	0
T22	7739	9	0	0
T23	1805	4	0	0
T24	1851	0	0	0
T28	0	5	0	0
T30	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	246437338	4011	0	0
g_div4.Div4Whole_A	246437338	4610	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246437338	4011	0	0
T1	28885	0	0	0
T2	626498	76	0	0
T3	0	11	0	0
T4	9445	0	0	0
T9	0	30	0	0
T16	944	3	0	0
T17	2713	0	0	0
T18	2482	8	0	0
T21	802	4	0	0
T22	4470	8	0	0
T23	913	3	0	0
T24	913	0	0	0
T28	0	3	0	0
T30	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246437338	4610	0	0
T1	28885	0	0	0
T2	626498	89	0	0
T3	0	16	0	0
T4	9445	0	0	0
T9	0	39	0	0
T16	944	8	0	0
T17	2713	0	0	0
T18	2482	9	0	0
T21	802	2	0	0
T22	4470	9	0	0
T23	913	4	0	0
T24	913	0	0	0
T28	0	5	0	0
T30	0	5	0	0