Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47354	0	0
CgEnOn_A	2147483647	38606	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47354	0	0
T1	370982	3	0	0
T2	4177960	475	0	0
T3	2058688	2	0	0
T4	203271	3	0	0
T9	3847815	102	0	0
T12	0	5	0	0
T16	12010	3	0	0
T17	61418	39	0	0
T18	48719	3	0	0
T19	930632	0	0	0
T20	6663	0	0	0
T21	3489	3	0	0
T22	18310	3	0	0
T23	4074	3	0	0
T24	11852	7	0	0
T28	8053	0	0	0
T29	17410	0	0	0
T45	0	5	0	0
T46	0	28	0	0
T47	0	25	0	0
T58	0	25	0	0
T132	0	10	0	0
T133	0	25	0	0
T134	0	20	0	0
T135	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38606	0	0
T1	370982	0	0	0
T2	4177960	457	0	0
T3	2587597	5	0	0
T4	203271	0	0	0
T9	4840331	201	0	0
T10	0	88	0	0
T12	0	4	0	0
T16	12010	0	0	0
T17	61418	36	0	0
T18	48719	0	0	0
T19	1153001	0	0	0
T20	6663	0	0	0
T24	11852	4	0	0
T28	8053	0	0	0
T29	17410	13	0	0
T45	0	8	0	0
T46	0	43	0	0
T47	0	25	0	0
T58	0	25	0	0
T101	0	9	0	0
T102	0	1	0	0
T103	0	9	0	0
T132	0	10	0	0
T133	0	25	0	0
T134	0	20	0	0
T135	0	5	0	0
T136	0	1	0	0
T139	0	38	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Unreachable
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	246436945	158	0	0
CgEnOn_A	246436945	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246436945	158	0	0
T2	626498	0	0	0
T3	117013	0	0	0
T4	9444	0	0	0
T9	217949	0	0	0
T12	0	1	0	0
T17	2713	4	0	0
T18	2482	0	0	0
T19	30351	0	0	0
T20	755	0	0	0
T28	936	0	0	0
T29	1981	0	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T58	0	5	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	4	0	0
T135	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246436945	158	0	0
T2	626498	0	0	0
T3	117013	0	0	0
T4	9444	0	0	0
T9	217949	0	0	0
T12	0	1	0	0
T17	2713	4	0	0
T18	2482	0	0	0
T19	30351	0	0	0
T20	755	0	0	0
T28	936	0	0	0
T29	1981	0	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T58	0	5	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	4	0	0
T135	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Unreachable
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	123217885	158	0	0
CgEnOn_A	123217885	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123217885	158	0	0
T2	313248	0	0	0
T3	58505	0	0	0
T4	4722	0	0	0
T9	108974	0	0	0
T12	0	1	0	0
T17	1356	4	0	0
T18	1239	0	0	0
T19	15176	0	0	0
T20	378	0	0	0
T28	468	0	0	0
T29	990	0	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T58	0	5	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	4	0	0
T135	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123217885	158	0	0
T2	313248	0	0	0
T3	58505	0	0	0
T4	4722	0	0	0
T9	108974	0	0	0
T12	0	1	0	0
T17	1356	4	0	0
T18	1239	0	0	0
T19	15176	0	0	0
T20	378	0	0	0
T28	468	0	0	0
T29	990	0	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T58	0	5	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	4	0	0
T135	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Unreachable
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	494351189	158	0	0
CgEnOn_A	494351189	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351189	158	0	0
T2	125253	0	0	0
T3	233670	0	0	0
T4	18913	0	0	0
T9	437194	0	0	0
T12	0	1	0	0
T17	5518	4	0	0
T18	4434	0	0	0
T19	117893	0	0	0
T20	1548	0	0	0
T28	1853	0	0	0
T29	4041	0	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T58	0	5	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	4	0	0
T135	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351189	153	0	0
T2	125253	0	0	0
T3	233670	0	0	0
T4	18913	0	0	0
T9	437194	0	0	0
T17	5518	4	0	0
T18	4434	0	0	0
T19	117893	0	0	0
T20	1548	0	0	0
T28	1853	0	0	0
T29	4041	0	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T58	0	5	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	4	0	0
T135	0	1	0	0
T136	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Unreachable
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524810617	128	0	0
CgEnOn_A	524810617	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	128	0	0
T2	131616	0	0	0
T3	255415	0	0	0
T4	19702	0	0	0
T9	477625	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T20	1613	0	0	0
T28	1930	0	0	0
T29	4209	0	0	0
T46	0	3	0	0
T47	0	5	0	0
T58	0	4	0	0
T132	0	1	0	0
T133	0	6	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	127	0	0
T2	131616	0	0	0
T3	255415	0	0	0
T4	19702	0	0	0
T9	477625	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T20	1613	0	0	0
T28	1930	0	0	0
T29	4209	0	0	0
T46	0	3	0	0
T47	0	5	0	0
T58	0	4	0	0
T132	0	1	0	0
T133	0	6	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Unreachable
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	123217885	158	0	0
CgEnOn_A	123217885	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123217885	158	0	0
T2	313248	0	0	0
T3	58505	0	0	0
T4	4722	0	0	0
T9	108974	0	0	0
T12	0	1	0	0
T17	1356	4	0	0
T18	1239	0	0	0
T19	15176	0	0	0
T20	378	0	0	0
T28	468	0	0	0
T29	990	0	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T58	0	5	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	4	0	0
T135	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123217885	158	0	0
T2	313248	0	0	0
T3	58505	0	0	0
T4	4722	0	0	0
T9	108974	0	0	0
T12	0	1	0	0
T17	1356	4	0	0
T18	1239	0	0	0
T19	15176	0	0	0
T20	378	0	0	0
T28	468	0	0	0
T29	990	0	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T58	0	5	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	4	0	0
T135	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Unreachable
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524810617	128	0	0
CgEnOn_A	524810617	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	128	0	0
T2	131616	0	0	0
T3	255415	0	0	0
T4	19702	0	0	0
T9	477625	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T20	1613	0	0	0
T28	1930	0	0	0
T29	4209	0	0	0
T46	0	3	0	0
T47	0	5	0	0
T58	0	4	0	0
T132	0	1	0	0
T133	0	6	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	127	0	0
T2	131616	0	0	0
T3	255415	0	0	0
T4	19702	0	0	0
T9	477625	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T20	1613	0	0	0
T28	1930	0	0	0
T29	4209	0	0	0
T46	0	3	0	0
T47	0	5	0	0
T58	0	4	0	0
T132	0	1	0	0
T133	0	6	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Unreachable
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	123217885	158	0	0
CgEnOn_A	123217885	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123217885	158	0	0
T2	313248	0	0	0
T3	58505	0	0	0
T4	4722	0	0	0
T9	108974	0	0	0
T12	0	1	0	0
T17	1356	4	0	0
T18	1239	0	0	0
T19	15176	0	0	0
T20	378	0	0	0
T28	468	0	0	0
T29	990	0	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T58	0	5	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	4	0	0
T135	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123217885	158	0	0
T2	313248	0	0	0
T3	58505	0	0	0
T4	4722	0	0	0
T9	108974	0	0	0
T12	0	1	0	0
T17	1356	4	0	0
T18	1239	0	0	0
T19	15176	0	0	0
T20	378	0	0	0
T28	468	0	0	0
T29	990	0	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T58	0	5	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	4	0	0
T135	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T45,T46
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	246436945	7549	0	0
CgEnOn_A	246436945	5365	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246436945	7549	0	0
T1	28884	1	0	0
T2	626498	131	0	0
T4	9444	1	0	0
T16	943	1	0	0
T17	2713	5	0	0
T18	2482	1	0	0
T21	802	1	0	0
T22	4469	1	0	0
T23	913	1	0	0
T24	913	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246436945	5365	0	0
T1	28884	0	0	0
T2	626498	125	0	0
T3	117013	1	0	0
T4	9444	0	0	0
T9	217949	31	0	0
T10	0	25	0	0
T16	943	0	0	0
T17	2713	4	0	0
T18	2482	0	0	0
T19	30351	0	0	0
T24	913	1	0	0
T29	0	4	0	0
T45	0	1	0	0
T46	0	5	0	0
T139	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T45,T46
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	123217885	7224	0	0
CgEnOn_A	123217885	5040	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123217885	7224	0	0
T1	14442	1	0	0
T2	313248	127	0	0
T4	4722	1	0	0
T16	470	1	0	0
T17	1356	5	0	0
T18	1239	1	0	0
T21	400	1	0	0
T22	2233	1	0	0
T23	455	1	0	0
T24	456	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123217885	5040	0	0
T1	14442	0	0	0
T2	313248	121	0	0
T3	58505	1	0	0
T4	4722	0	0	0
T9	108974	25	0	0
T10	0	26	0	0
T16	470	0	0	0
T17	1356	4	0	0
T18	1239	0	0	0
T19	15176	0	0	0
T24	456	1	0	0
T29	0	4	0	0
T45	0	1	0	0
T46	0	5	0	0
T139	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T45,T46
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	494351189	7679	0	0
CgEnOn_A	494351189	5492	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351189	7679	0	0
T1	57820	1	0	0
T2	125253	132	0	0
T4	18913	1	0	0
T16	1870	1	0	0
T17	5518	5	0	0
T18	4434	1	0	0
T21	1525	1	0	0
T22	7739	1	0	0
T23	1804	1	0	0
T24	1850	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351189	5492	0	0
T1	57820	0	0	0
T2	125253	126	0	0
T3	233670	1	0	0
T4	18913	0	0	0
T9	437194	43	0	0
T10	0	27	0	0
T16	1870	0	0	0
T17	5518	4	0	0
T18	4434	0	0	0
T19	117893	0	0	0
T24	1850	1	0	0
T29	0	5	0	0
T45	0	1	0	0
T46	0	5	0	0
T139	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T46,T47
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	252037411	7548	0	0
CgEnOn_A	252037411	5360	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252037411	7548	0	0
T1	28912	1	0	0
T2	631770	128	0	0
T4	9457	1	0	0
T16	935	1	0	0
T17	2914	4	0	0
T18	2217	1	0	0
T21	762	1	0	0
T22	3869	1	0	0
T23	902	1	0	0
T24	925	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252037411	5360	0	0
T1	28912	0	0	0
T2	631770	122	0	0
T3	119721	1	0	0
T4	9457	0	0	0
T9	228399	32	0	0
T10	0	27	0	0
T16	935	0	0	0
T17	2914	3	0	0
T18	2217	0	0	0
T19	58949	0	0	0
T24	925	1	0	0
T29	0	5	0	0
T46	0	5	0	0
T47	0	4	0	0
T139	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Covered	T24,T2,T3
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524810617	4072	0	0
CgEnOn_A	524810617	4072	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	4072	0	0
T1	60231	0	0	0
T2	131616	85	0	0
T3	255415	2	0	0
T4	19702	0	0	0
T9	477625	102	0	0
T10	0	10	0	0
T16	1948	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T46	0	3	0	0
T101	0	9	0	0
T102	0	1	0	0
T103	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	4072	0	0
T1	60231	0	0	0
T2	131616	85	0	0
T3	255415	2	0	0
T4	19702	0	0	0
T9	477625	102	0	0
T10	0	10	0	0
T16	1948	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T46	0	3	0	0
T101	0	9	0	0
T102	0	1	0	0
T103	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Covered	T24,T2,T3
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524810617	4067	0	0
CgEnOn_A	524810617	4067	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	4067	0	0
T1	60231	0	0	0
T2	131616	90	0	0
T3	255415	2	0	0
T4	19702	0	0	0
T9	477625	102	0	0
T10	0	12	0	0
T16	1948	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T46	0	3	0	0
T101	0	8	0	0
T102	0	1	0	0
T103	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	4067	0	0
T1	60231	0	0	0
T2	131616	90	0	0
T3	255415	2	0	0
T4	19702	0	0	0
T9	477625	102	0	0
T10	0	12	0	0
T16	1948	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T46	0	3	0	0
T101	0	8	0	0
T102	0	1	0	0
T103	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Covered	T24,T2,T3
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524810617	4027	0	0
CgEnOn_A	524810617	4028	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	4027	0	0
T1	60231	0	0	0
T2	131616	92	0	0
T3	255415	3	0	0
T4	19702	0	0	0
T9	477625	108	0	0
T10	0	8	0	0
T16	1948	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T46	0	3	0	0
T101	0	9	0	0
T102	0	1	0	0
T103	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	4028	0	0
T1	60231	0	0	0
T2	131616	92	0	0
T3	255415	3	0	0
T4	19702	0	0	0
T9	477625	108	0	0
T10	0	8	0	0
T16	1948	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T46	0	3	0	0
T101	0	9	0	0
T102	0	1	0	0
T103	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T2,T3
1	0	Covered	T24,T2,T3
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524810617	4142	0	0
CgEnOn_A	524810617	4143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	4142	0	0
T1	60231	0	0	0
T2	131616	86	0	0
T3	255415	1	0	0
T4	19702	0	0	0
T9	477625	102	0	0
T10	0	12	0	0
T16	1948	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T46	0	3	0	0
T101	0	7	0	0
T102	0	1	0	0
T103	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524810617	4143	0	0
T1	60231	0	0	0
T2	131616	86	0	0
T3	255415	1	0	0
T4	19702	0	0	0
T9	477625	102	0	0
T10	0	12	0	0
T16	1948	0	0	0
T17	6103	4	0	0
T18	4619	0	0	0
T19	122810	0	0	0
T24	1927	1	0	0
T46	0	3	0	0
T101	0	7	0	0
T102	0	1	0	0
T103	0	8	0	0