Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T17,T2
0	1	Covered	T2,T3,T9
1	0	Covered	T21,T22,T23

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T3
1	0	Covered	T17,T45,T46
1	1	Covered	T21,T22,T23

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1116045065	14054	0	0
GateOpen_A	1116045065	14052	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116045065	14054	0	0
T1	130061	0	0	0
T2	1696769	312	0	0
T3	528911	0	0	0
T4	42538	0	0	0
T9	992516	91	0	0
T10	0	79	0	0
T12	0	13	0	0
T16	4220	0	0	0
T17	12503	15	0	0
T18	10373	0	0	0
T19	222372	0	0	0
T24	4146	4	0	0
T29	0	13	0	0
T45	0	3	0	0
T46	0	20	0	0
T47	0	19	0	0
T139	0	41	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116045065	14052	0	0
T1	130061	0	0	0
T2	1696769	312	0	0
T3	528911	0	0	0
T4	42538	0	0	0
T9	992516	91	0	0
T10	0	79	0	0
T12	0	13	0	0
T16	4220	0	0	0
T17	12503	15	0	0
T18	10373	0	0	0
T19	222372	0	0	0
T24	4146	4	0	0
T29	0	13	0	0
T45	0	3	0	0
T46	0	20	0	0
T47	0	19	0	0
T139	0	41	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T17,T2
0	1	Covered	T2,T3,T9
1	0	Covered	T21,T22,T23

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T3
1	0	Covered	T17,T45,T46
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	123218297	3444	0	0
GateOpen_A	123218297	3443	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123218297	3444	0	0
T1	14443	0	0	0
T2	313248	77	0	0
T3	58505	0	0	0
T4	4723	0	0	0
T9	108974	13	0	0
T10	0	19	0	0
T16	470	0	0	0
T17	1357	4	0	0
T18	1239	0	0	0
T19	15177	0	0	0
T24	457	1	0	0
T29	0	4	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T139	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123218297	3443	0	0
T1	14443	0	0	0
T2	313248	77	0	0
T3	58505	0	0	0
T4	4723	0	0	0
T9	108974	13	0	0
T10	0	19	0	0
T16	470	0	0	0
T17	1357	4	0	0
T18	1239	0	0	0
T19	15177	0	0	0
T24	457	1	0	0
T29	0	4	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T139	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T17,T2
0	1	Covered	T2,T3,T9
1	0	Covered	T21,T22,T23

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T3
1	0	Covered	T17,T45,T46
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	246437338	3542	0	0
GateOpen_A	246437338	3542	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246437338	3542	0	0
T1	28885	0	0	0
T2	626498	80	0	0
T3	117014	0	0	0
T4	9445	0	0	0
T9	217949	25	0	0
T10	0	20	0	0
T16	944	0	0	0
T17	2713	4	0	0
T18	2482	0	0	0
T19	30351	0	0	0
T24	913	1	0	0
T29	0	4	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T139	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	246437338	3542	0	0
T1	28885	0	0	0
T2	626498	80	0	0
T3	117014	0	0	0
T4	9445	0	0	0
T9	217949	25	0	0
T10	0	20	0	0
T16	944	0	0	0
T17	2713	4	0	0
T18	2482	0	0	0
T19	30351	0	0	0
T24	913	1	0	0
T29	0	4	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T139	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T17,T2
0	1	Covered	T2,T3,T9
1	0	Covered	T21,T22,T23

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T3
1	0	Covered	T17,T45,T46
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	494351619	3546	0	0
GateOpen_A	494351619	3545	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351619	3546	0	0
T1	57821	0	0	0
T2	125253	75	0	0
T3	233671	0	0	0
T4	18913	0	0	0
T9	437194	25	0	0
T10	0	20	0	0
T16	1871	0	0	0
T17	5519	4	0	0
T18	4435	0	0	0
T19	117894	0	0	0
T24	1851	1	0	0
T29	0	2	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T139	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494351619	3545	0	0
T1	57821	0	0	0
T2	125253	75	0	0
T3	233671	0	0	0
T4	18913	0	0	0
T9	437194	25	0	0
T10	0	20	0	0
T16	1871	0	0	0
T17	5519	4	0	0
T18	4435	0	0	0
T19	117894	0	0	0
T24	1851	1	0	0
T29	0	2	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	5	0	0
T139	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T17,T2
0	1	Covered	T2,T3,T9
1	0	Covered	T21,T22,T23

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T2,T3
1	0	Covered	T17,T46,T47
1	1	Covered	T21,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	252037811	3522	0	0
GateOpen_A	252037811	3522	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252037811	3522	0	0
T1	28912	0	0	0
T2	631770	80	0	0
T3	119721	0	0	0
T4	9457	0	0	0
T9	228399	28	0	0
T10	0	20	0	0
T12	0	13	0	0
T16	935	0	0	0
T17	2914	3	0	0
T18	2217	0	0	0
T19	58950	0	0	0
T24	925	1	0	0
T29	0	3	0	0
T46	0	5	0	0
T47	0	4	0	0
T139	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252037811	3522	0	0
T1	28912	0	0	0
T2	631770	80	0	0
T3	119721	0	0	0
T4	9457	0	0	0
T9	228399	28	0	0
T10	0	20	0	0
T12	0	13	0	0
T16	935	0	0	0
T17	2914	3	0	0
T18	2217	0	0	0
T19	58950	0	0	0
T24	925	1	0	0
T29	0	3	0	0
T46	0	5	0	0
T47	0	4	0	0
T139	0	10	0	0