Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	558632	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3102477

1

T4

341

T6

3

T7

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	903321	1			T4	342		T30	94		T31	639
values[0x0]	1267961	1			T4	287		T6	9		T7	19
values[0x1]	1489827	1			T4	292		T6	7		T7	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	313314	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3347795

1

T4

454

T6

5

T7

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14289	1			T36	1		T44	5		T61	1
valid_sources[0x01]	12060	1			T30	2		T44	1		T63	4
valid_sources[0x02]	15164	1			T36	1		T61	1		T63	1
valid_sources[0x03]	14037	1			T30	1		T61	2		T63	3
valid_sources[0x04]	17080	1			T30	1		T31	18		T36	4
valid_sources[0x05]	13886	1			T30	2		T31	3		T36	1
valid_sources[0x06]	14115	1			T31	8		T36	2		T61	1
valid_sources[0x07]	13319	1			T31	3		T36	1		T61	3
valid_sources[0x08]	14094	1			T30	1		T31	10		T36	1
valid_sources[0x09]	13605	1			T30	3		T63	2		T46	4
valid_sources[0x0a]	13804	1			T31	8		T36	1		T61	1
valid_sources[0x0b]	12896	1			T30	2		T36	3		T44	3
valid_sources[0x0c]	14135	1			T30	1		T36	2		T61	1
valid_sources[0x0d]	13677	1			T31	4		T61	2		T63	2
valid_sources[0x0e]	14536	1			T30	4		T36	1		T44	2
valid_sources[0x0f]	15795	1			T31	24		T36	2		T44	1
valid_sources[0x10]	14857	1			T44	3		T61	1		T63	5
valid_sources[0x11]	14263	1			T35	128		T63	16		T64	2
valid_sources[0x12]	13700	1			T36	2		T61	1		T62	1
valid_sources[0x13]	14363	1			T30	2		T36	1		T61	1
valid_sources[0x14]	14140	1			T30	5		T63	4		T46	6
valid_sources[0x15]	14335	1			T30	1		T31	20		T36	2
valid_sources[0x16]	13969	1			T36	1		T44	1		T63	1
valid_sources[0x17]	14313	1			T31	12		T61	1		T63	7
valid_sources[0x18]	15554	1			T31	14		T35	128		T61	1
valid_sources[0x19]	14989	1			T30	1		T36	3		T44	3
valid_sources[0x1a]	14191	1			T31	33		T63	3		T64	1
valid_sources[0x1b]	13943	1			T31	23		T36	1		T63	3
valid_sources[0x1c]	14303	1			T30	2		T31	11		T61	2
valid_sources[0x1d]	16348	1			T30	3		T36	2		T61	1
valid_sources[0x1e]	13573	1			T30	2		T36	1		T63	3
valid_sources[0x1f]	18061	1			T4	921		T30	1		T31	3
valid_sources[0x20]	13528	1			T30	3		T36	1		T61	2
valid_sources[0x21]	14334	1			T46	1		T85	12		T65	6
valid_sources[0x22]	15465	1			T30	1		T63	2		T46	1
valid_sources[0x23]	13555	1			T30	8		T31	5		T63	9
valid_sources[0x24]	14023	1			T30	2		T34	3		T61	1
valid_sources[0x25]	13163	1			T30	6		T61	1		T63	2
valid_sources[0x26]	14337	1			T30	1		T36	3		T62	1
valid_sources[0x27]	13454	1			T30	5		T61	2		T63	1
valid_sources[0x28]	15505	1			T30	1		T63	9		T65	7
valid_sources[0x29]	14209	1			T36	1		T63	4		T46	12
valid_sources[0x2a]	16819	1			T34	24		T63	1		T45	1
valid_sources[0x2b]	14945	1			T30	1		T35	192		T61	3
valid_sources[0x2c]	14609	1			T35	128		T36	1		T63	3
valid_sources[0x2d]	15057	1			T61	2		T62	1		T63	2
valid_sources[0x2e]	14538	1			T30	6		T36	2		T44	1
valid_sources[0x2f]	12947	1			T30	1		T61	3		T63	2
valid_sources[0x30]	14072	1			T31	18		T61	2		T63	2
valid_sources[0x31]	12841	1			T30	1		T61	1		T62	1
valid_sources[0x32]	13782	1			T30	2		T31	5		T44	2
valid_sources[0x33]	14346	1			T30	1		T63	3		T64	1
valid_sources[0x34]	13992	1			T36	1		T61	3		T63	3
valid_sources[0x35]	13297	1			T30	9		T36	1		T63	2
valid_sources[0x36]	14629	1			T30	4		T36	1		T61	1
valid_sources[0x37]	13358	1			T30	2		T36	1		T61	1
valid_sources[0x38]	14559	1			T30	2		T36	1		T62	1
valid_sources[0x39]	12557	1			T36	3		T63	4		T65	3
valid_sources[0x3a]	14376	1			T30	7		T61	1		T63	1
valid_sources[0x3b]	13515	1			T30	1		T31	18		T36	1
valid_sources[0x3c]	13275	1			T63	3		T46	5		T64	2
valid_sources[0x3d]	14963	1			T6	16		T36	1		T61	2
valid_sources[0x3e]	14206	1			T30	7		T36	4		T44	1
valid_sources[0x3f]	14108	1			T31	3		T63	2		T74	2
valid_sources[0x40]	14773	1			T31	2		T61	1		T63	4
valid_sources[0x41]	13496	1			T31	5		T36	1		T63	5
valid_sources[0x42]	13646	1			T61	1		T63	3		T75	2
valid_sources[0x43]	15578	1			T30	2		T36	4		T63	2
valid_sources[0x44]	15193	1			T30	8		T31	3		T44	1
valid_sources[0x45]	13966	1			T30	2		T36	2		T62	1
valid_sources[0x46]	14520	1			T30	5		T36	1		T63	3
valid_sources[0x47]	15306	1			T36	1		T61	2		T45	3
valid_sources[0x48]	14519	1			T30	1		T31	7		T36	1
valid_sources[0x49]	15200	1			T31	10		T36	1		T61	1
valid_sources[0x4a]	14113	1			T36	1		T63	3		T64	1
valid_sources[0x4b]	14014	1			T31	8		T36	1		T44	2
valid_sources[0x4c]	14536	1			T30	2		T44	2		T61	1
valid_sources[0x4d]	13512	1			T30	13		T31	1		T44	8
valid_sources[0x4e]	14354	1			T30	2		T31	13		T36	2
valid_sources[0x4f]	14207	1			T30	1		T31	7		T61	3
valid_sources[0x50]	14952	1			T30	3		T36	2		T61	1
valid_sources[0x51]	15195	1			T31	8		T36	3		T61	1
valid_sources[0x52]	15797	1			T31	20		T34	6		T36	1
valid_sources[0x53]	15127	1			T30	3		T61	3		T63	2
valid_sources[0x54]	14759	1			T30	2		T34	3		T35	128
valid_sources[0x55]	14042	1			T36	2		T61	1		T64	1
valid_sources[0x56]	15232	1			T30	3		T44	1		T63	2
valid_sources[0x57]	14450	1			T30	1		T63	4		T74	3
valid_sources[0x58]	13196	1			T30	5		T61	1		T63	4
valid_sources[0x59]	12999	1			T31	14		T36	1		T63	5
valid_sources[0x5a]	14436	1			T30	2		T31	9		T36	1
valid_sources[0x5b]	14176	1			T63	6		T46	7		T64	1
valid_sources[0x5c]	12855	1			T31	22		T61	2		T63	2
valid_sources[0x5d]	15002	1			T30	3		T31	6		T61	3
valid_sources[0x5e]	14087	1			T30	3		T31	11		T35	192
valid_sources[0x5f]	14023	1			T30	2		T35	128		T36	1
valid_sources[0x60]	13265	1			T30	1		T36	1		T44	1
valid_sources[0x61]	13829	1			T30	3		T61	3		T63	6
valid_sources[0x62]	13357	1			T30	1		T36	1		T44	1
valid_sources[0x63]	14215	1			T30	1		T62	1		T63	3
valid_sources[0x64]	13768	1			T30	2		T31	6		T61	1
valid_sources[0x65]	15692	1			T31	6		T36	1		T61	1
valid_sources[0x66]	14722	1			T44	1		T61	1		T45	1
valid_sources[0x67]	14114	1			T31	11		T34	2		T35	192
valid_sources[0x68]	14477	1			T30	2		T31	7		T36	1
valid_sources[0x69]	13028	1			T30	4		T31	13		T36	1
valid_sources[0x6a]	15808	1			T30	2		T36	1		T63	3
valid_sources[0x6b]	15059	1			T31	6		T44	2		T61	2
valid_sources[0x6c]	14339	1			T36	1		T63	2		T46	5
valid_sources[0x6d]	14078	1			T63	5		T46	5		T45	3
valid_sources[0x6e]	14517	1			T30	4		T34	5		T36	1
valid_sources[0x6f]	14309	1			T7	8		T30	4		T36	1
valid_sources[0x70]	14019	1			T63	5		T64	4		T45	1
valid_sources[0x71]	14836	1			T30	5		T36	1		T61	2
valid_sources[0x72]	13428	1			T7	6		T31	31		T36	3
valid_sources[0x73]	15075	1			T30	2		T31	6		T34	11
valid_sources[0x74]	13887	1			T30	1		T44	1		T63	1
valid_sources[0x75]	13634	1			T36	4		T44	1		T61	1
valid_sources[0x76]	13918	1			T7	2		T30	1		T36	1
valid_sources[0x77]	15070	1			T30	1		T61	3		T63	2
valid_sources[0x78]	14930	1			T31	5		T63	1		T64	1
valid_sources[0x79]	14912	1			T30	2		T31	13		T61	2
valid_sources[0x7a]	14346	1			T34	13		T63	5		T46	4
valid_sources[0x7b]	14874	1			T30	3		T31	5		T34	2
valid_sources[0x7c]	15629	1			T30	3		T36	2		T61	1
valid_sources[0x7d]	14776	1			T30	7		T31	5		T36	1
valid_sources[0x7e]	13970	1			T30	1		T36	2		T62	1
valid_sources[0x7f]	14493	1			T30	1		T36	1		T61	2
valid_sources[0x80]	13804	1			T30	1		T31	5		T63	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

784033

1

T4

148

T30

89

T31

89

values[0x0]

all_enables

biggest_size

1180011

1

T4

131

T6

2

T7

9

values[0x1]

all_enables

biggest_size

1138433

1

T4

62

T6

1

T7

3