Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

Group : clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
TransAes	100.00	1	100	1	64	64
TransHmac	100.00	1	100	1	64	64
TransKmac	100.00	1	100	1	64	64
TransOtbn	100.00	1	100	1	64	64

---

Group Instance : TransAes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransAes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransAes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransAes

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransHmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransHmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransHmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransHmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransKmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransKmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransKmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransKmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransOtbn

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransOtbn

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransOtbn

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransOtbn

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1664569

1

T4

10567

T6

2

T7

2

auto[1]

495740515

1

T4

216883

T6

1592

T7

4171

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

434015379

1

T4

218528

T6

30

T7

3005

auto[1]

63389705

1

T4

8922

T6

1564

T7

1168

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9961

1

T4

20

T6

2

T7

2

auto[1]

497395123

1

T4

227430

T6

1592

T7

4171

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267998892

1

T4

197043

T6

1564

T7

3188

auto[1]

229406192

1

T4

30407

T6

30

T7

985

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2968

1

T31

40

T61

20

T46

2

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T162

2

T159

2

T163

2

auto[0]

auto[1]

auto[0]

auto[0]

537183

1

T4

5394

T164

2647

T165

209

auto[0]

auto[1]

auto[0]

auto[1]

519438

1

T4

353

T31

5130

T34

4188

auto[0]

auto[1]

auto[1]

auto[0]

508255

1

T4

3327

T166

738

T1

3543

auto[0]

auto[1]

auto[1]

auto[1]

92573

1

T4

1473

T1

615

T16

46

auto[1]

auto[1]

auto[0]

auto[0]

224379022

1

T4

186613

T7

2656

T30

10

auto[1]

auto[1]

auto[0]

auto[1]

42554890

1

T4

4673

T6

1564

T7

532

auto[1]

auto[1]

auto[1]

auto[0]

208585544

1

T4

23174

T6

28

T7

347

auto[1]

auto[1]

auto[1]

auto[1]

20218218

1

T4

2423

T7

636

T23

229

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1518582

1

T4

9239

T6

2

T7

2

auto[1]

495886502

1

T4

218211

T6

1592

T7

4171

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

416018460

1

T4

212458

T6

30

T7

3245

auto[1]

81386624

1

T4

14992

T6

1564

T7

928

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9961

1

T4

20

T6

2

T7

2

auto[1]

497395123

1

T4

227430

T6

1592

T7

4171

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267998892

1

T4

197043

T6

1564

T7

3188

auto[1]

229406192

1

T4

30407

T6

30

T7

985

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2978

1

T31

40

T61

20

T46

2

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T3

2

T10

2

T12

2

auto[0]

auto[1]

auto[0]

auto[0]

483377

1

T4

5299

T165

209

T1

2545

auto[0]

auto[1]

auto[0]

auto[1]

465145

1

T4

594

T31

6506

T34

3753

auto[0]

auto[1]

auto[1]

auto[0]

470987

1

T4

2780

T1

3025

T16

242

auto[0]

auto[1]

auto[1]

auto[1]

91953

1

T4

546

T1

893

T16

81

auto[1]

auto[1]

auto[0]

auto[0]

212257843

1

T4

183282

T7

2700

T30

10

auto[1]

auto[1]

auto[0]

auto[1]

54784168

1

T4

7858

T6

1564

T7

488

auto[1]

auto[1]

auto[1]

auto[0]

202800560

1

T4

21077

T6

28

T7

543

auto[1]

auto[1]

auto[1]

auto[1]

26041090

1

T4

5994

T7

440

T23

229

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1412683

1

T4

7961

T6

2

T7

2

auto[1]

495992401

1

T4

219489

T6

1592

T7

4171

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

436680892

1

T4

211973

T6

30

T7

587

auto[1]

60724192

1

T4

15477

T6

1564

T7

3586

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9961

1

T4

20

T6

2

T7

2

auto[1]

497395123

1

T4

227430

T6

1592

T7

4171

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267998892

1

T4

197043

T6

1564

T7

3188

auto[1]

229406192

1

T4

30407

T6

30

T7

985

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2958

1

T31

40

T61

20

T46

2

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T10

2

T159

2

T163

4

auto[0]

auto[1]

auto[0]

auto[0]

423395

1

T4

4311

T1

1946

T16

124

auto[0]

auto[1]

auto[0]

auto[1]

452092

1

T4

504

T31

5614

T34

435

auto[0]

auto[1]

auto[1]

auto[0]

435658

1

T4

2585

T1

2244

T16

227

auto[0]

auto[1]

auto[1]

auto[1]

94418

1

T4

541

T1

662

T16

23

auto[1]

auto[1]

auto[0]

auto[0]

221100799

1

T4

183796

T7

150

T30

10

auto[1]

auto[1]

auto[0]

auto[1]

46014247

1

T4

8422

T6

1564

T7

3038

auto[1]

auto[1]

auto[1]

auto[0]

214715377

1

T4

21261

T6

28

T7

435

auto[1]

auto[1]

auto[1]

auto[1]

14159137

1

T4

6010

T7

548

T23

158

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1334833

1

T4

6637

T6

2

T7

2

auto[1]

496070251

1

T4

220813

T6

1592

T7

4171

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

428232246

1

T4

216694

T6

30

T7

3191

auto[1]

69172838

1

T4

10756

T6

1564

T7

982

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9961

1

T4

20

T6

2

T7

2

auto[1]

497395123

1

T4

227430

T6

1592

T7

4171

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267998892

1

T4

197043

T6

1564

T7

3188

auto[1]

229406192

1

T4

30407

T6

30

T7

985

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2942

1

T31

40

T61

20

T46

2

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T162

2

T159

4

T167

2

auto[0]

auto[1]

auto[0]

auto[0]

388814

1

T4

2761

T164

2647

T165

209

auto[0]

auto[1]

auto[0]

auto[1]

469390

1

T4

665

T31

7374

T34

435

auto[0]

auto[1]

auto[1]

auto[0]

373404

1

T4

2195

T1

2910

T16

271

auto[0]

auto[1]

auto[1]

auto[1]

96105

1

T4

996

T1

709

T22

135

auto[1]

auto[1]

auto[0]

auto[0]

222571982

1

T4

186468

T7

2630

T30

10

auto[1]

auto[1]

auto[0]

auto[1]

44560347

1

T4

7139

T6

1564

T7

558

auto[1]

auto[1]

auto[1]

auto[0]

204892496

1

T4

25250

T6

28

T7

559

auto[1]

auto[1]

auto[1]

auto[1]

24042585

1

T4

1956

T7

424

T24

176

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded