Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	697779310	68342	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697779310	68342	0	0
T1	856750	992	0	0
T2	1149825	425	0	0
T3	0	2128	0	0
T5	1030990	0	0	0
T9	0	109	0	0
T10	0	1296	0	0
T11	0	2636	0	0
T12	0	1595	0	0
T13	0	200	0	0
T14	0	51	0	0
T15	0	177	0	0
T16	18690	0	0	0
T17	12230	0	0	0
T18	7015	0	0	0
T19	7630	0	0	0
T20	6060	0	0	0
T21	11705	0	0	0
T22	7500	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	139555862	10317	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	10317	0	0
T1	171350	137	0	0
T2	229965	70	0	0
T3	0	408	0	0
T5	206198	0	0	0
T9	0	14	0	0
T10	0	204	0	0
T11	0	421	0	0
T12	0	244	0	0
T13	0	34	0	0
T14	0	8	0	0
T15	0	35	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T21	2341	0	0	0
T22	1500	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	139555862	13714	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	13714	0	0
T1	171350	198	0	0
T2	229965	85	0	0
T3	0	408	0	0
T5	206198	0	0	0
T9	0	23	0	0
T10	0	261	0	0
T11	0	532	0	0
T12	0	314	0	0
T13	0	41	0	0
T14	0	10	0	0
T15	0	35	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T21	2341	0	0	0
T22	1500	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	139555862	20467	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	20467	0	0
T1	171350	317	0	0
T2	229965	119	0	0
T3	0	496	0	0
T5	206198	0	0	0
T9	0	37	0	0
T10	0	367	0	0
T11	0	737	0	0
T12	0	473	0	0
T13	0	51	0	0
T14	0	15	0	0
T15	0	37	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T21	2341	0	0	0
T22	1500	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	139555862	10138	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	10138	0	0
T1	171350	138	0	0
T2	229965	66	0	0
T3	0	408	0	0
T5	206198	0	0	0
T9	0	14	0	0
T10	0	201	0	0
T11	0	411	0	0
T12	0	242	0	0
T13	0	34	0	0
T14	0	8	0	0
T15	0	35	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T21	2341	0	0	0
T22	1500	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	139555862	13706	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	13706	0	0
T1	171350	202	0	0
T2	229965	85	0	0
T3	0	408	0	0
T5	206198	0	0	0
T9	0	21	0	0
T10	0	263	0	0
T11	0	535	0	0
T12	0	322	0	0
T13	0	40	0	0
T14	0	10	0	0
T15	0	35	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T21	2341	0	0	0
T22	1500	0	0	0