Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_io_step_down_req_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div2_div_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div4_div_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_main_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_usb_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_io_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_usb_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_step_down_req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_div2_div_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_div4_div_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_main_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div2_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div4_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_usb_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div2_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div4_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_main_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_usb_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_io_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_step_down_req_sync

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync

Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_div2_div_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_div_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_usb_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_calib_rdy_sync

Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 6 6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_main_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_usb_meas.u_calib_rdy_sync

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Cond Coverage for Module : prim_mubi4_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7
Branch Coverage for Module : prim_mubi4_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 22484 22484 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 837335172 825834762 0 14454
gen_flops.gen_stable_chks.OutputDelay_A 2147483647 2147483647 0 16863
gen_flops.gen_stable_chks.OutputIfUnstable_A 2147483647 190293 0 0
gen_no_flops.OutputDelay_A 2147483647 2147483647 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22484 22484 0 0
T1 28 28 0 0
T4 28 28 0 0
T5 28 28 0 0
T6 28 28 0 0
T7 28 28 0 0
T16 28 28 0 0
T17 28 28 0 0
T23 28 28 0 0
T24 28 28 0 0
T25 28 28 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6514714 6467945 0 0
T4 3477451 3454241 0 0
T5 5111466 5107600 0 0
T6 41165 37410 0 0
T7 66006 65269 0 0
T16 98045 94669 0 0
T17 158679 155557 0 0
T23 88875 86107 0 0
T24 63991 59517 0 0
T25 71272 67784 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 837335172 825834762 0 14454
T1 1028100 1018866 0 18
T4 288696 286488 0 18
T5 1237188 1236240 0 18
T6 8424 7542 0 18
T7 6336 6240 0 18
T16 22428 21576 0 18
T17 14676 14334 0 18
T23 8028 7710 0 18
T24 14466 13380 0 18
T25 16332 15474 0 18

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 16863
T1 1781820 1766270 0 21
T4 1239055 1229250 0 21
T5 1328572 1327472 0 21
T6 11622 10405 0 21
T7 23082 22763 0 21
T16 26204 25207 0 21
T17 55459 54209 0 21
T23 30353 29180 0 21
T24 17147 15862 0 21
T25 18946 17950 0 21

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 190293 0 0
T1 1781820 1967 0 0
T2 0 469 0 0
T4 1239055 526 0 0
T5 1328572 4 0 0
T6 11622 12 0 0
T7 23082 66 0 0
T16 26204 231 0 0
T17 55459 244 0 0
T18 1403 29 0 0
T20 0 41 0 0
T23 29015 89 0 0
T24 17147 208 0 0
T25 18946 242 0 0
T105 0 146 0 0
T106 0 10 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3704794 3682788 0 0
T4 1949700 1938113 0 0
T5 2545706 2543849 0 0
T6 21119 19424 0 0
T7 36588 36227 0 0
T16 49413 47847 0 0
T17 88544 86975 0 0
T23 50494 49178 0 0
T24 32378 30236 0 0
T25 35994 34321 0 0

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T23,T24 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T23,T24 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T23,T24 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T23,T24
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T23,T24
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T23,T24
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T23,T24
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T23,T24
0 Covered T4,T6,T7

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 468720198 465062230 0 0
gen_flops.gen_stable_chks.OutputDelay_A 468720198 465055102 0 2409
gen_flops.gen_stable_chks.OutputIfUnstable_A 468720198 26745 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468720198 465062230 0 0
T1 267852 266173 0 0
T4 225831 224104 0 0
T5 163384 163235 0 0
T6 1706 1530 0 0
T7 4058 4006 0 0
T16 3624 3490 0 0
T17 9787 9570 0 0
T23 5357 5153 0 0
T24 2385 2209 0 0
T25 2614 2479 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468720198 465055102 0 2409
T1 267852 266172 0 3
T4 225831 224074 0 3
T5 163384 163232 0 3
T6 1706 1527 0 3
T7 4058 4003 0 3
T16 3624 3487 0 3
T17 9787 9567 0 3
T23 5357 5150 0 3
T24 2385 2206 0 3
T25 2614 2476 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468720198 26745 0 0
T1 267852 322 0 0
T2 0 186 0 0
T4 225831 62 0 0
T5 163384 0 0 0
T6 1706 0 0 0
T7 4058 0 0 0
T16 3624 0 0 0
T17 9787 98 0 0
T18 0 13 0 0
T20 0 19 0 0
T23 5357 21 0 0
T24 2385 93 0 0
T25 2614 100 0 0
T105 0 60 0 0

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_no_flops.OutputDelay_A 139555862 137646354 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_no_flops.OutputDelay_A 139555862 137646354 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T24,T25 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T24,T25 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T24,T25 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T24,T25
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T24,T25
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T24,T25
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T24,T25
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T24,T25
0 Covered T4,T6,T7

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_flops.gen_stable_chks.OutputDelay_A 139555862 137639127 0 2409
gen_flops.gen_stable_chks.OutputIfUnstable_A 139555862 16439 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137639127 0 2409
T1 171350 169811 0 3
T4 48116 47748 0 3
T5 206198 206040 0 3
T6 1404 1257 0 3
T7 1056 1040 0 3
T16 3738 3596 0 3
T17 2446 2389 0 3
T23 1338 1285 0 3
T24 2411 2230 0 3
T25 2722 2579 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 16439 0 0
T1 171350 192 0 0
T2 0 139 0 0
T4 48116 37 0 0
T5 206198 0 0 0
T6 1404 0 0 0
T7 1056 0 0 0
T16 3738 0 0 0
T17 2446 36 0 0
T18 1403 3 0 0
T20 0 4 0 0
T24 2411 34 0 0
T25 2722 32 0 0
T105 0 41 0 0
T106 0 10 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T23,T24 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T23,T24 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T23,T24 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T23,T24
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T23,T24
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T23,T24
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T23,T24
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T23,T24
0 Covered T4,T6,T7

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_flops.gen_stable_chks.OutputDelay_A 139555862 137639127 0 2409
gen_flops.gen_stable_chks.OutputIfUnstable_A 139555862 18568 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137639127 0 2409
T1 171350 169811 0 3
T4 48116 47748 0 3
T5 206198 206040 0 3
T6 1404 1257 0 3
T7 1056 1040 0 3
T16 3738 3596 0 3
T17 2446 2389 0 3
T23 1338 1285 0 3
T24 2411 2230 0 3
T25 2722 2579 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 18568 0 0
T1 171350 260 0 0
T2 0 144 0 0
T4 48116 34 0 0
T5 206198 0 0 0
T6 1404 0 0 0
T7 1056 0 0 0
T16 3738 0 0 0
T17 2446 41 0 0
T18 0 13 0 0
T20 0 18 0 0
T23 1338 20 0 0
T24 2411 26 0 0
T25 2722 38 0 0
T105 0 45 0 0

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 498457097 496527386 0 0
gen_no_flops.OutputDelay_A 498457097 496527386 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 496527386 0 0
T1 292817 291743 0 0
T4 229248 228277 0 0
T5 188198 188072 0 0
T6 1777 1736 0 0
T7 4228 4202 0 0
T16 3776 3707 0 0
T17 10195 10055 0 0
T23 5580 5511 0 0
T24 2485 2345 0 0
T25 2722 2610 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 496527386 0 0
T1 292817 291743 0 0
T4 229248 228277 0 0
T5 188198 188072 0 0
T6 1777 1736 0 0
T7 4228 4202 0 0
T16 3776 3707 0 0
T17 10195 10055 0 0
T23 5580 5511 0 0
T24 2485 2345 0 0
T25 2722 2610 0 0

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 468720198 466912245 0 0
gen_no_flops.OutputDelay_A 468720198 466912245 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468720198 466912245 0 0
T1 267852 267445 0 0
T4 225831 224900 0 0
T5 163384 163263 0 0
T6 1706 1667 0 0
T7 4058 4033 0 0
T16 3624 3558 0 0
T17 9787 9653 0 0
T23 5357 5291 0 0
T24 2385 2250 0 0
T25 2614 2506 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 468720198 466912245 0 0
T1 267852 267445 0 0
T4 225831 224900 0 0
T5 163384 163263 0 0
T6 1706 1667 0 0
T7 4058 4033 0 0
T16 3624 3558 0 0
T17 9787 9653 0 0
T23 5357 5291 0 0
T24 2385 2250 0 0
T25 2614 2506 0 0

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 233763307 233763307 0 0
gen_no_flops.OutputDelay_A 233763307 233763307 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233763307 233763307 0 0
T1 133939 133939 0 0
T4 113502 113502 0 0
T5 81632 81632 0 0
T6 834 834 0 0
T7 2017 2017 0 0
T16 1779 1779 0 0
T17 5476 5476 0 0
T23 4354 4354 0 0
T24 1274 1274 0 0
T25 1422 1422 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233763307 233763307 0 0
T1 133939 133939 0 0
T4 113502 113502 0 0
T5 81632 81632 0 0
T6 834 834 0 0
T7 2017 2017 0 0
T16 1779 1779 0 0
T17 5476 5476 0 0
T23 4354 4354 0 0
T24 1274 1274 0 0
T25 1422 1422 0 0

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 116881047 116881047 0 0
gen_no_flops.OutputDelay_A 116881047 116881047 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 116881047 116881047 0 0
T1 669688 669688 0 0
T4 56751 56751 0 0
T5 40816 40816 0 0
T6 417 417 0 0
T7 1008 1008 0 0
T16 890 890 0 0
T17 2737 2737 0 0
T23 2177 2177 0 0
T24 635 635 0 0
T25 709 709 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 116881047 116881047 0 0
T1 669688 669688 0 0
T4 56751 56751 0 0
T5 40816 40816 0 0
T6 417 417 0 0
T7 1008 1008 0 0
T16 890 890 0 0
T17 2737 2737 0 0
T23 2177 2177 0 0
T24 635 635 0 0
T25 709 709 0 0

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 239030054 238106445 0 0
gen_no_flops.OutputDelay_A 239030054 238106445 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239030054 238106445 0 0
T1 141130 140615 0 0
T4 118680 118215 0 0
T5 81696 81636 0 0
T6 853 834 0 0
T7 2029 2017 0 0
T16 1812 1779 0 0
T17 4893 4826 0 0
T23 2678 2645 0 0
T24 1193 1126 0 0
T25 1307 1254 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239030054 238106445 0 0
T1 141130 140615 0 0
T4 118680 118215 0 0
T5 81696 81636 0 0
T6 853 834 0 0
T7 2029 2017 0 0
T16 1812 1779 0 0
T17 4893 4826 0 0
T23 2678 2645 0 0
T24 1193 1126 0 0
T25 1307 1254 0 0

Line Coverage for Instance : tb.dut.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 6 6

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 139555862 137639127 0 2409


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137639127 0 2409
T1 171350 169811 0 3
T4 48116 47748 0 3
T5 206198 206040 0 3
T6 1404 1257 0 3
T7 1056 1040 0 3
T16 3738 3596 0 3
T17 2446 2389 0 3
T23 1338 1285 0 3
T24 2411 2230 0 3
T25 2722 2579 0 3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 139555862 137639127 0 2409


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137639127 0 2409
T1 171350 169811 0 3
T4 48116 47748 0 3
T5 206198 206040 0 3
T6 1404 1257 0 3
T7 1056 1040 0 3
T16 3738 3596 0 3
T17 2446 2389 0 3
T23 1338 1285 0 3
T24 2411 2230 0 3
T25 2722 2579 0 3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 139555862 137639127 0 2409


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137639127 0 2409
T1 171350 169811 0 3
T4 48116 47748 0 3
T5 206198 206040 0 3
T6 1404 1257 0 3
T7 1056 1040 0 3
T16 3738 3596 0 3
T17 2446 2389 0 3
T23 1338 1285 0 3
T24 2411 2230 0 3
T25 2722 2579 0 3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 139555862 137639127 0 2409


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137639127 0 2409
T1 171350 169811 0 3
T4 48116 47748 0 3
T5 206198 206040 0 3
T6 1404 1257 0 3
T7 1056 1040 0 3
T16 3738 3596 0 3
T17 2446 2389 0 3
T23 1338 1285 0 3
T24 2411 2230 0 3
T25 2722 2579 0 3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 139555862 137639127 0 2409


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137639127 0 2409
T1 171350 169811 0 3
T4 48116 47748 0 3
T5 206198 206040 0 3
T6 1404 1257 0 3
T7 1056 1040 0 3
T16 3738 3596 0 3
T17 2446 2389 0 3
T23 1338 1285 0 3
T24 2411 2230 0 3
T25 2722 2579 0 3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 139555862 137639127 0 2409


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137639127 0 2409
T1 171350 169811 0 3
T4 48116 47748 0 3
T5 206198 206040 0 3
T6 1404 1257 0 3
T7 1056 1040 0 3
T16 3738 3596 0 3
T17 2446 2389 0 3
T23 1338 1285 0 3
T24 2411 2230 0 3
T25 2722 2579 0 3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_no_flops.OutputDelay_A 139555862 137646354 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_no_flops.OutputDelay_A 139555862 137646354 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_no_flops.OutputDelay_A 139555862 137646354 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 139555862 137646354 0 0
gen_no_flops.OutputDelay_A 139555862 137646354 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 139555862 137646354 0 0
T1 171350 169813 0 0
T4 48116 47778 0 0
T5 206198 206043 0 0
T6 1404 1260 0 0
T7 1056 1043 0 0
T16 3738 3599 0 0
T17 2446 2392 0 0
T23 1338 1288 0 0
T24 2411 2233 0 0
T25 2722 2582 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 498457097 494569259 0 0
gen_flops.gen_stable_chks.OutputDelay_A 498457097 494562108 0 2409
gen_flops.gen_stable_chks.OutputIfUnstable_A 498457097 31985 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494562108 0 2409
T1 292817 290119 0 3
T4 229248 227420 0 3
T5 188198 188040 0 3
T6 1777 1591 0 3
T7 4228 4170 0 3
T16 3776 3632 0 3
T17 10195 9966 0 3
T23 5580 5365 0 3
T24 2485 2299 0 3
T25 2722 2579 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 31985 0 0
T1 292817 310 0 0
T4 229248 113 0 0
T5 188198 1 0 0
T6 1777 3 0 0
T7 4228 16 0 0
T16 3776 56 0 0
T17 10195 23 0 0
T23 5580 12 0 0
T24 2485 11 0 0
T25 2722 18 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 498457097 494569259 0 0
gen_no_flops.OutputDelay_A 498457097 494569259 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 498457097 494569259 0 0
gen_flops.gen_stable_chks.OutputDelay_A 498457097 494562108 0 2409
gen_flops.gen_stable_chks.OutputIfUnstable_A 498457097 32037 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494562108 0 2409
T1 292817 290119 0 3
T4 229248 227420 0 3
T5 188198 188040 0 3
T6 1777 1591 0 3
T7 4228 4170 0 3
T16 3776 3632 0 3
T17 10195 9966 0 3
T23 5580 5365 0 3
T24 2485 2299 0 3
T25 2722 2579 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 32037 0 0
T1 292817 277 0 0
T4 229248 104 0 0
T5 188198 1 0 0
T6 1777 3 0 0
T7 4228 20 0 0
T16 3776 61 0 0
T17 10195 15 0 0
T23 5580 12 0 0
T24 2485 16 0 0
T25 2722 20 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 498457097 494569259 0 0
gen_no_flops.OutputDelay_A 498457097 494569259 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 498457097 494569259 0 0
gen_flops.gen_stable_chks.OutputDelay_A 498457097 494562108 0 2409
gen_flops.gen_stable_chks.OutputIfUnstable_A 498457097 32169 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494562108 0 2409
T1 292817 290119 0 3
T4 229248 227420 0 3
T5 188198 188040 0 3
T6 1777 1591 0 3
T7 4228 4170 0 3
T16 3776 3632 0 3
T17 10195 9966 0 3
T23 5580 5365 0 3
T24 2485 2299 0 3
T25 2722 2579 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 32169 0 0
T1 292817 295 0 0
T4 229248 81 0 0
T5 188198 1 0 0
T6 1777 3 0 0
T7 4228 14 0 0
T16 3776 59 0 0
T17 10195 19 0 0
T23 5580 12 0 0
T24 2485 15 0 0
T25 2722 16 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 498457097 494569259 0 0
gen_no_flops.OutputDelay_A 498457097 494569259 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7 

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT4,T6,T7
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7 



	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T4,T6,T7

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 498457097 494569259 0 0
gen_flops.gen_stable_chks.OutputDelay_A 498457097 494562108 0 2409
gen_flops.gen_stable_chks.OutputIfUnstable_A 498457097 32350 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494562108 0 2409
T1 292817 290119 0 3
T4 229248 227420 0 3
T5 188198 188040 0 3
T6 1777 1591 0 3
T7 4228 4170 0 3
T16 3776 3632 0 3
T17 10195 9966 0 3
T23 5580 5365 0 3
T24 2485 2299 0 3
T25 2722 2579 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 32350 0 0
T1 292817 311 0 0
T4 229248 95 0 0
T5 188198 1 0 0
T6 1777 3 0 0
T7 4228 16 0 0
T16 3776 55 0 0
T17 10195 12 0 0
T23 5580 12 0 0
T24 2485 13 0 0
T25 2722 18 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 803 803 0 0
OutputsKnown_A 498457097 494569259 0 0
gen_no_flops.OutputDelay_A 498457097 494569259 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 803 803 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 498457097 494569259 0 0
T1 292817 290120 0 0
T4 229248 227450 0 0
T5 188198 188043 0 0
T6 1777 1594 0 0
T7 4228 4173 0 0
T16 3776 3635 0 0
T17 10195 9969 0 0
T23 5580 5368 0 0
T24 2485 2302 0 0
T25 2722 2582 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%