Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	139555862	137515256	0	0
AllClkBypReqTrue_A	139555862	128722	0	0
IoClkBypReqFalse_A	139555862	137437730	0	2409
IoClkBypReqTrue_A	139555862	201496	0	0
LcClkBypAckFalse_A	139555862	137527129	0	0
LcClkBypAckTrue_A	139555862	116849	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	137515256	0	0
T1	171350	169532	0	0
T4	48116	47488	0	0
T5	206198	206042	0	0
T6	1404	1259	0	0
T7	1056	1042	0	0
T16	3738	3598	0	0
T17	2446	1961	0	0
T23	1338	1259	0	0
T24	2411	2033	0	0
T25	2722	2258	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	128722	0	0
T1	171350	2809	0	0
T2	0	929	0	0
T4	48116	280	0	0
T5	206198	0	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T16	3738	0	0	0
T17	2446	430	0	0
T18	0	36	0	0
T20	0	49	0	0
T23	1338	28	0	0
T24	2411	199	0	0
T25	2722	323	0	0
T105	0	371	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	137437730	0	2409
T1	171350	169466	0	3
T4	48116	47255	0	3
T5	206198	206040	0	3
T6	1404	1257	0	3
T7	1056	1040	0	3
T16	3738	3596	0	3
T17	2446	1851	0	3
T23	1338	1285	0	3
T24	2411	1748	0	3
T25	2722	2089	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	201496	0	0
T1	171350	3457	0	0
T2	0	1424	0	0
T4	48116	493	0	0
T5	206198	0	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T16	3738	0	0	0
T17	2446	538	0	0
T18	1403	23	0	0
T20	0	26	0	0
T24	2411	482	0	0
T25	2722	490	0	0
T105	0	619	0	0
T106	0	157	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	137527129	0	0
T1	171350	169621	0	0
T4	48116	47465	0	0
T5	206198	206042	0	0
T6	1404	1259	0	0
T7	1056	1042	0	0
T16	3738	3598	0	0
T17	2446	2144	0	0
T23	1338	1287	0	0
T24	2411	1986	0	0
T25	2722	2289	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139555862	116849	0	0
T1	171350	1912	0	0
T2	0	978	0	0
T4	48116	303	0	0
T5	206198	0	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T16	3738	0	0	0
T17	2446	247	0	0
T18	1403	20	0	0
T24	2411	246	0	0
T25	2722	292	0	0
T105	0	342	0	0
T106	0	85	0	0
T107	0	241	0	0