Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1993830120	15438	0	0
TransStop_A	1993830120	7866	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1993830120	15438	0	0
T1	1171268	153	0	0
T2	0	156	0	0
T4	916992	76	0	0
T5	752796	0	0	0
T6	7112	0	0	0
T7	16912	0	0	0
T16	15104	30	0	0
T17	40784	0	0	0
T18	5668	0	0	0
T19	12452	15	0	0
T20	97020	0	0	0
T21	0	4	0	0
T22	0	18	0	0
T108	0	4	0	0
T109	0	26	0	0
T110	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1993830120	7866	0	0
T1	1171268	69	0	0
T2	0	89	0	0
T4	916992	40	0	0
T5	752796	0	0	0
T6	7112	0	0	0
T7	16912	0	0	0
T16	15104	14	0	0
T17	40784	0	0	0
T18	5668	0	0	0
T19	12452	5	0	0
T20	97020	0	0	0
T21	0	4	0	0
T22	0	5	0	0
T108	0	4	0	0
T109	0	14	0	0
T110	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	498457530	3844	0	0
TransStop_A	498457530	1983	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457530	3844	0	0
T1	292817	38	0	0
T2	0	38	0	0
T4	229248	19	0	0
T5	188199	0	0	0
T6	1778	0	0	0
T7	4228	0	0	0
T16	3776	6	0	0
T17	10196	0	0	0
T18	1417	0	0	0
T19	3113	3	0	0
T20	24255	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T108	0	1	0	0
T109	0	8	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457530	1983	0	0
T1	292817	19	0	0
T2	0	27	0	0
T4	229248	8	0	0
T5	188199	0	0	0
T6	1778	0	0	0
T7	4228	0	0	0
T16	3776	3	0	0
T17	10196	0	0	0
T18	1417	0	0	0
T19	3113	1	0	0
T20	24255	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T108	0	1	0	0
T109	0	5	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	498457530	3875	0	0
TransStop_A	498457530	1975	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457530	3875	0	0
T1	292817	38	0	0
T2	0	42	0	0
T4	229248	19	0	0
T5	188199	0	0	0
T6	1778	0	0	0
T7	4228	0	0	0
T16	3776	11	0	0
T17	10196	0	0	0
T18	1417	0	0	0
T19	3113	4	0	0
T20	24255	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T108	0	1	0	0
T109	0	4	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457530	1975	0	0
T1	292817	17	0	0
T2	0	24	0	0
T4	229248	11	0	0
T5	188199	0	0	0
T6	1778	0	0	0
T7	4228	0	0	0
T16	3776	6	0	0
T17	10196	0	0	0
T18	1417	0	0	0
T19	3113	1	0	0
T20	24255	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	498457530	3857	0	0
TransStop_A	498457530	1937	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457530	3857	0	0
T1	292817	33	0	0
T2	0	40	0	0
T4	229248	19	0	0
T5	188199	0	0	0
T6	1778	0	0	0
T7	4228	0	0	0
T16	3776	6	0	0
T17	10196	0	0	0
T18	1417	0	0	0
T19	3113	4	0	0
T20	24255	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T108	0	1	0	0
T109	0	6	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457530	1937	0	0
T1	292817	16	0	0
T2	0	18	0	0
T4	229248	11	0	0
T5	188199	0	0	0
T6	1778	0	0	0
T7	4228	0	0	0
T16	3776	2	0	0
T17	10196	0	0	0
T18	1417	0	0	0
T19	3113	2	0	0
T20	24255	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T108	0	1	0	0
T109	0	4	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	498457530	3862	0	0
TransStop_A	498457530	1971	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457530	3862	0	0
T1	292817	44	0	0
T2	0	36	0	0
T4	229248	19	0	0
T5	188199	0	0	0
T6	1778	0	0	0
T7	4228	0	0	0
T16	3776	7	0	0
T17	10196	0	0	0
T18	1417	0	0	0
T19	3113	4	0	0
T20	24255	0	0	0
T21	0	1	0	0
T22	0	6	0	0
T108	0	1	0	0
T109	0	8	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457530	1971	0	0
T1	292817	17	0	0
T2	0	20	0	0
T4	229248	10	0	0
T5	188199	0	0	0
T6	1778	0	0	0
T7	4228	0	0	0
T16	3776	3	0	0
T17	10196	0	0	0
T18	1417	0	0	0
T19	3113	1	0	0
T20	24255	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T108	0	1	0	0
T109	0	4	0	0
T110	0	1	0	0