Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	140500063	4540882	0	0
clk_enables_rd_A	140500063	39941	0	0
clk_hints_rd_A	140500063	36506	0	0
extclk_ctrl_rd_A	140500063	45929	0	0
extclk_ctrl_regwen_rd_A	140500063	33881	0	0
jitter_enable_rd_A	140500063	54039	0	0
jitter_regwen_rd_A	140500063	38083	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	4540882	0	0
T30	9506	544	0	0
T31	12217	6	0	0
T44	2112	188	0	0
T45	2183	59	0	0
T64	6270	216	0	0
T65	10168	0	0	0
T74	8284	4	0	0
T75	3581	244	0	0
T76	0	554	0	0
T77	0	664	0	0
T84	1476	0	0	0
T85	7256	5	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	39941	0	0
T4	48116	9	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T30	9506	16	0	0
T31	12217	206	0	0
T47	0	48	0	0
T61	7519	50	0	0
T64	6270	6	0	0
T74	8284	91	0	0
T86	6597	144	0	0
T87	5175	0	0	0
T92	0	2	0	0
T133	0	56	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	36506	0	0
T4	48116	14	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T30	9506	8	0	0
T31	12217	232	0	0
T47	0	10	0	0
T61	7519	30	0	0
T64	6270	16	0	0
T74	8284	86	0	0
T86	6597	103	0	0
T87	5175	0	0	0
T92	0	25	0	0
T133	0	50	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	45929	0	0
T4	48116	46	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T30	9506	48	0	0
T47	0	21	0	0
T61	7519	34	0	0
T64	6270	11	0	0
T68	0	18	0	0
T80	0	18	0	0
T86	6597	138	0	0
T87	5175	0	0	0
T88	18554	0	0	0
T89	789	0	0	0
T92	0	6	0	0
T133	0	84	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	33881	0	0
T30	9506	21	0	0
T31	12217	90	0	0
T47	0	22	0	0
T61	7519	44	0	0
T64	6270	12	0	0
T74	8284	31	0	0
T86	6597	132	0	0
T87	5175	0	0	0
T88	18554	0	0	0
T89	789	0	0	0
T90	766	0	0	0
T92	0	14	0	0
T133	0	56	0	0
T141	0	5	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	54039	0	0
T4	48116	491	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T30	9506	19	0	0
T31	12217	68	0	0
T47	0	33	0	0
T61	7519	43	0	0
T64	6270	16	0	0
T74	8284	49	0	0
T86	6597	114	0	0
T87	5175	0	0	0
T133	0	78	0	0
T147	0	9	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	38083	0	0
T30	9506	26	0	0
T31	12217	67	0	0
T47	0	33	0	0
T61	7519	30	0	0
T64	6270	9	0	0
T74	8284	37	0	0
T86	6597	147	0	0
T87	5175	0	0	0
T88	18554	0	0	0
T89	789	0	0	0
T90	766	0	0	0
T92	0	7	0	0
T133	0	71	0	0
T141	0	1	0	0