Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T31,T34,T35
1	0	Covered	T4,T31,T34

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1405000630	1239416	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1405000630	261567	0	0
SrcBusyKnown_A	1405000630	1384783450	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1405000630	1239416	0	0
T1	856750	9260	0	0
T2	0	5298	0	0
T3	0	9649	0	0
T4	481160	798	0	0
T5	1030990	1461	0	0
T6	14040	0	0	0
T7	10560	0	0	0
T9	0	1602	0	0
T10	0	8737	0	0
T11	0	17208	0	0
T16	18690	0	0	0
T17	12230	0	0	0
T18	7015	0	0	0
T19	7630	0	0	0
T20	6060	0	0	0
T26	0	2942	0	0
T28	0	253	0	0
T31	61085	1845	0	0
T34	4655	113	0	0
T35	87175	3470	0	0
T36	11245	283	0	0
T44	10560	38	0	0
T46	0	689	0	0
T61	37595	801	0	0
T62	7775	154	0	0
T63	0	902	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	1488024	1478044	0	0
T6	11174	10074	0	0
T7	26680	26372	0	0
T30	62486	61788	0	0
T31	158250	139828	0	0
T32	26278	25394	0	0
T33	7426	6864	0	0
T34	29396	28728	0	0
T35	423736	422928	0	0
T36	59200	58802	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1405000630	261567	0	0
T1	856750	1660	0	0
T2	0	1440	0	0
T3	0	3651	0	0
T4	481160	240	0	0
T5	1030990	170	0	0
T6	14040	0	0	0
T7	10560	0	0	0
T9	0	200	0	0
T10	0	2505	0	0
T11	0	4975	0	0
T16	18690	0	0	0
T17	12230	0	0	0
T18	7015	0	0	0
T19	7630	0	0	0
T20	6060	0	0	0
T26	0	585	0	0
T28	0	30	0	0
T31	61085	348	0	0
T34	4655	36	0	0
T35	87175	960	0	0
T36	11245	78	0	0
T44	10560	7	0	0
T46	0	179	0	0
T61	37595	97	0	0
T62	7775	20	0	0
T63	0	180	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1405000630	1384783450	0	0
T4	481160	477780	0	0
T6	14040	12600	0	0
T7	10560	10430	0	0
T30	95060	93850	0	0
T31	122170	106270	0	0
T32	7530	7230	0	0
T33	11610	10650	0	0
T34	9310	9090	0	0
T35	174350	173980	0	0
T36	22490	22320	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140500063	79226	0	0
DstReqKnown_A	471635496	467784533	0	0
SrcAckBusyChk_A	140500063	23511	0	0
SrcBusyKnown_A	140500063	138478345	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	79226	0	0
T1	171350	1257	0	0
T2	0	774	0	0
T3	0	1855	0	0
T4	48116	63	0	0
T5	206198	178	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T9	0	200	0	0
T10	0	1299	0	0
T11	0	2542	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T26	0	416	0	0
T28	0	36	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471635496	467784533	0	0
T4	225831	224104	0	0
T6	1706	1530	0	0
T7	4058	4006	0	0
T30	9506	9385	0	0
T31	24432	21238	0	0
T32	4019	3857	0	0
T33	1137	1043	0	0
T34	4471	4364	0	0
T35	64376	64241	0	0
T36	8998	8932	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	23511	0	0
T1	171350	332	0	0
T2	0	288	0	0
T3	0	731	0	0
T4	48116	24	0	0
T5	206198	34	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T9	0	40	0	0
T10	0	501	0	0
T11	0	996	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T26	0	117	0	0
T28	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	138478345	0	0
T4	48116	47778	0	0
T6	1404	1260	0	0
T7	1056	1043	0	0
T30	9506	9385	0	0
T31	12217	10627	0	0
T32	753	723	0	0
T33	1161	1065	0	0
T34	931	909	0	0
T35	17435	17398	0	0
T36	2249	2232	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140500063	111244	0	0
DstReqKnown_A	235173102	234198909	0	0
SrcAckBusyChk_A	140500063	23509	0	0
SrcBusyKnown_A	140500063	138478345	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	111244	0	0
T1	171350	1850	0	0
T2	0	1098	0	0
T3	0	1852	0	0
T4	48116	84	0	0
T5	206198	287	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T9	0	326	0	0
T10	0	1797	0	0
T11	0	3573	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T26	0	593	0	0
T28	0	52	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235173102	234198909	0	0
T4	113502	113102	0	0
T6	834	765	0	0
T7	2017	2003	0	0
T30	4720	4692	0	0
T31	11349	10617	0	0
T32	1949	1928	0	0
T33	549	521	0	0
T34	2223	2182	0	0
T35	32162	32121	0	0
T36	4487	4466	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	23509	0	0
T1	171350	332	0	0
T2	0	288	0	0
T3	0	730	0	0
T4	48116	24	0	0
T5	206198	34	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T9	0	40	0	0
T10	0	501	0	0
T11	0	995	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T26	0	117	0	0
T28	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	138478345	0	0
T4	48116	47778	0	0
T6	1404	1260	0	0
T7	1056	1043	0	0
T30	9506	9385	0	0
T31	12217	10627	0	0
T32	753	723	0	0
T33	1161	1065	0	0
T34	931	909	0	0
T35	17435	17398	0	0
T36	2249	2232	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140500063	173874	0	0
DstReqKnown_A	117585969	117098983	0	0
SrcAckBusyChk_A	140500063	23509	0	0
SrcBusyKnown_A	140500063	138478345	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	173874	0	0
T1	171350	3043	0	0
T2	0	1558	0	0
T3	0	2238	0	0
T4	48116	111	0	0
T5	206198	502	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T9	0	568	0	0
T10	0	2596	0	0
T11	0	5066	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T26	0	930	0	0
T28	0	88	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117585969	117098983	0	0
T4	56751	56550	0	0
T6	417	383	0	0
T7	1008	1001	0	0
T30	2360	2346	0	0
T31	5676	5309	0	0
T32	975	965	0	0
T33	275	261	0	0
T34	1112	1091	0	0
T35	16081	16060	0	0
T36	2243	2233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	23509	0	0
T1	171350	332	0	0
T2	0	288	0	0
T3	0	730	0	0
T4	48116	24	0	0
T5	206198	34	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T9	0	40	0	0
T10	0	501	0	0
T11	0	995	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T26	0	117	0	0
T28	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	138478345	0	0
T4	48116	47778	0	0
T6	1404	1260	0	0
T7	1056	1043	0	0
T30	9506	9385	0	0
T31	12217	10627	0	0
T32	753	723	0	0
T33	1161	1065	0	0
T34	931	909	0	0
T35	17435	17398	0	0
T36	2249	2232	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140500063	77760	0	0
DstReqKnown_A	501493983	497405084	0	0
SrcAckBusyChk_A	140500063	23508	0	0
SrcBusyKnown_A	140500063	138478345	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	77760	0	0
T1	171350	1257	0	0
T2	0	769	0	0
T3	0	1852	0	0
T4	48116	63	0	0
T5	206198	206	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T9	0	197	0	0
T10	0	1255	0	0
T11	0	2476	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T26	0	412	0	0
T28	0	29	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501493983	497405084	0	0
T4	229248	227450	0	0
T6	1777	1594	0	0
T7	4228	4173	0	0
T30	9904	9778	0	0
T31	25451	22123	0	0
T32	4187	4018	0	0
T33	1184	1086	0	0
T34	4657	4545	0	0
T35	67060	66920	0	0
T36	9373	9304	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	23508	0	0
T1	171350	332	0	0
T2	0	288	0	0
T3	0	730	0	0
T4	48116	24	0	0
T5	206198	34	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T9	0	40	0	0
T10	0	501	0	0
T11	0	995	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T26	0	117	0	0
T28	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	138478345	0	0
T4	48116	47778	0	0
T6	1404	1260	0	0
T7	1056	1043	0	0
T30	9506	9385	0	0
T31	12217	10627	0	0
T32	753	723	0	0
T33	1161	1065	0	0
T34	931	909	0	0
T35	17435	17398	0	0
T36	2249	2232	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140500063	109222	0	0
DstReqKnown_A	240487723	238530042	0	0
SrcAckBusyChk_A	140500063	23085	0	0
SrcBusyKnown_A	140500063	138478345	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	109222	0	0
T1	171350	1853	0	0
T2	0	1099	0	0
T3	0	1852	0	0
T4	48116	81	0	0
T5	206198	288	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T9	0	311	0	0
T10	0	1790	0	0
T11	0	3551	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T26	0	591	0	0
T28	0	48	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240487723	238530042	0	0
T4	118680	117816	0	0
T6	853	765	0	0
T7	2029	2003	0	0
T30	4753	4693	0	0
T31	12217	10627	0	0
T32	2009	1929	0	0
T33	568	521	0	0
T34	2235	2182	0	0
T35	32189	32122	0	0
T36	4499	4466	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	23085	0	0
T1	171350	332	0	0
T2	0	288	0	0
T3	0	730	0	0
T4	48116	24	0	0
T5	206198	34	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T9	0	40	0	0
T10	0	501	0	0
T11	0	994	0	0
T16	3738	0	0	0
T17	2446	0	0	0
T18	1403	0	0	0
T19	1526	0	0	0
T20	1212	0	0	0
T26	0	117	0	0
T28	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	138478345	0	0
T4	48116	47778	0	0
T6	1404	1260	0	0
T7	1056	1043	0	0
T30	9506	9385	0	0
T31	12217	10627	0	0
T32	753	723	0	0
T33	1161	1065	0	0
T34	931	909	0	0
T35	17435	17398	0	0
T36	2249	2232	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T31,T34,T35
1	0	Covered	T4,T31,T34

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140500063	97845	0	0
DstReqKnown_A	471635496	467784533	0	0
SrcAckBusyChk_A	140500063	28882	0	0
SrcBusyKnown_A	140500063	138478345	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	97845	0	0
T4	48116	63	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T31	12217	252	0	0
T34	931	17	0	0
T35	17435	526	0	0
T36	2249	72	0	0
T44	2112	11	0	0
T46	0	75	0	0
T61	7519	42	0	0
T62	1555	18	0	0
T63	0	124	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471635496	467784533	0	0
T4	225831	224104	0	0
T6	1706	1530	0	0
T7	4058	4006	0	0
T30	9506	9385	0	0
T31	24432	21238	0	0
T32	4019	3857	0	0
T33	1137	1043	0	0
T34	4471	4364	0	0
T35	64376	64241	0	0
T36	8998	8932	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	28882	0	0
T4	48116	24	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T31	12217	71	0	0
T34	931	7	0	0
T35	17435	192	0	0
T36	2249	28	0	0
T44	2112	3	0	0
T46	0	28	0	0
T61	7519	9	0	0
T62	1555	4	0	0
T63	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	138478345	0	0
T4	48116	47778	0	0
T6	1404	1260	0	0
T7	1056	1043	0	0
T30	9506	9385	0	0
T31	12217	10627	0	0
T32	753	723	0	0
T33	1161	1065	0	0
T34	931	909	0	0
T35	17435	17398	0	0
T36	2249	2232	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T31,T34,T35
1	0	Covered	T4,T31,T34

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140500063	137551	0	0
DstReqKnown_A	235173102	234198909	0	0
SrcAckBusyChk_A	140500063	28919	0	0
SrcBusyKnown_A	140500063	138478345	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	137551	0	0
T4	48116	81	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T31	12217	376	0	0
T34	931	23	0	0
T35	17435	708	0	0
T36	2249	18	0	0
T44	2112	6	0	0
T46	0	176	0	0
T61	7519	141	0	0
T62	1555	30	0	0
T63	0	180	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235173102	234198909	0	0
T4	113502	113102	0	0
T6	834	765	0	0
T7	2017	2003	0	0
T30	4720	4692	0	0
T31	11349	10617	0	0
T32	1949	1928	0	0
T33	549	521	0	0
T34	2223	2182	0	0
T35	32162	32121	0	0
T36	4487	4466	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	28919	0	0
T4	48116	24	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T31	12217	72	0	0
T34	931	7	0	0
T35	17435	192	0	0
T36	2249	5	0	0
T44	2112	1	0	0
T46	0	45	0	0
T61	7519	18	0	0
T62	1555	4	0	0
T63	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	138478345	0	0
T4	48116	47778	0	0
T6	1404	1260	0	0
T7	1056	1043	0	0
T30	9506	9385	0	0
T31	12217	10627	0	0
T32	753	723	0	0
T33	1161	1065	0	0
T34	931	909	0	0
T35	17435	17398	0	0
T36	2249	2232	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T31,T34,T35
1	0	Covered	T4,T31,T34

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140500063	219090	0	0
DstReqKnown_A	117585969	117098983	0	0
SrcAckBusyChk_A	140500063	29119	0	0
SrcBusyKnown_A	140500063	138478345	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	219090	0	0
T4	48116	107	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T31	12217	539	0	0
T34	931	29	0	0
T35	17435	1025	0	0
T36	2249	148	0	0
T44	2112	10	0	0
T46	0	285	0	0
T61	7519	329	0	0
T62	1555	52	0	0
T63	0	293	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117585969	117098983	0	0
T4	56751	56550	0	0
T6	417	383	0	0
T7	1008	1001	0	0
T30	2360	2346	0	0
T31	5676	5309	0	0
T32	975	965	0	0
T33	275	261	0	0
T34	1112	1091	0	0
T35	16081	16060	0	0
T36	2243	2233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	29119	0	0
T4	48116	24	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T31	12217	66	0	0
T34	931	7	0	0
T35	17435	192	0	0
T36	2249	29	0	0
T44	2112	1	0	0
T46	0	53	0	0
T61	7519	24	0	0
T62	1555	4	0	0
T63	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	138478345	0	0
T4	48116	47778	0	0
T6	1404	1260	0	0
T7	1056	1043	0	0
T30	9506	9385	0	0
T31	12217	10627	0	0
T32	753	723	0	0
T33	1161	1065	0	0
T34	931	909	0	0
T35	17435	17398	0	0
T36	2249	2232	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T31,T34,T35
1	0	Covered	T4,T31,T34

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140500063	96221	0	0
DstReqKnown_A	501493983	497405084	0	0
SrcAckBusyChk_A	140500063	28884	0	0
SrcBusyKnown_A	140500063	138478345	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	96221	0	0
T4	48116	63	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T31	12217	241	0	0
T34	931	20	0	0
T35	17435	501	0	0
T36	2249	34	0	0
T44	2112	4	0	0
T46	0	107	0	0
T61	7519	114	0	0
T62	1555	22	0	0
T63	0	124	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501493983	497405084	0	0
T4	229248	227450	0	0
T6	1777	1594	0	0
T7	4228	4173	0	0
T30	9904	9778	0	0
T31	25451	22123	0	0
T32	4187	4018	0	0
T33	1184	1086	0	0
T34	4657	4545	0	0
T35	67060	66920	0	0
T36	9373	9304	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	28884	0	0
T4	48116	24	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T31	12217	68	0	0
T34	931	8	0	0
T35	17435	192	0	0
T36	2249	13	0	0
T44	2112	1	0	0
T46	0	40	0	0
T61	7519	23	0	0
T62	1555	4	0	0
T63	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	138478345	0	0
T4	48116	47778	0	0
T6	1404	1260	0	0
T7	1056	1043	0	0
T30	9506	9385	0	0
T31	12217	10627	0	0
T32	753	723	0	0
T33	1161	1065	0	0
T34	931	909	0	0
T35	17435	17398	0	0
T36	2249	2232	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T31,T34,T35
1	0	Covered	T4,T31,T34

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T31,T34
1	1	Covered	T4,T31,T34

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T6,T7
0	1	-	Covered	T4,T31,T34
0	0	1	Covered	T4,T31,T34
0	0	0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	140500063	137383	0	0
DstReqKnown_A	240487723	238530042	0	0
SrcAckBusyChk_A	140500063	28641	0	0
SrcBusyKnown_A	140500063	138478345	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	137383	0	0
T4	48116	82	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T31	12217	437	0	0
T34	931	24	0	0
T35	17435	710	0	0
T36	2249	11	0	0
T44	2112	7	0	0
T46	0	46	0	0
T61	7519	175	0	0
T62	1555	32	0	0
T63	0	181	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240487723	238530042	0	0
T4	118680	117816	0	0
T6	853	765	0	0
T7	2029	2003	0	0
T30	4753	4693	0	0
T31	12217	10627	0	0
T32	2009	1929	0	0
T33	568	521	0	0
T34	2235	2182	0	0
T35	32189	32122	0	0
T36	4499	4466	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	28641	0	0
T4	48116	24	0	0
T6	1404	0	0	0
T7	1056	0	0	0
T31	12217	71	0	0
T34	931	7	0	0
T35	17435	192	0	0
T36	2249	3	0	0
T44	2112	1	0	0
T46	0	13	0	0
T61	7519	23	0	0
T62	1555	4	0	0
T63	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140500063	138478345	0	0
T4	48116	47778	0	0
T6	1404	1260	0	0
T7	1056	1043	0	0
T30	9506	9385	0	0
T31	12217	10627	0	0
T32	753	723	0	0
T33	1161	1065	0	0
T34	931	909	0	0
T35	17435	17398	0	0
T36	2249	2232	0	0