Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T23,T24
1	1	Covered	T4,T23,T24

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	468720624	4301	0	0
g_div2.Div2Whole_A	468720624	5034	0	0
g_div4.Div4Stepped_A	233763711	4210	0	0
g_div4.Div4Whole_A	233763711	4780	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468720624	4301	0	0
T1	267852	51	0	0
T2	0	41	0	0
T4	225832	13	0	0
T5	163385	0	0	0
T6	1706	0	0	0
T7	4059	0	0	0
T16	3624	0	0	0
T17	9787	13	0	0
T18	0	1	0	0
T20	0	4	0	0
T23	5357	1	0	0
T24	2386	7	0	0
T25	2614	10	0	0
T105	0	9	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468720624	5034	0	0
T1	267852	58	0	0
T2	0	43	0	0
T4	225832	13	0	0
T5	163385	0	0	0
T6	1706	0	0	0
T7	4059	0	0	0
T16	3624	0	0	0
T17	9787	14	0	0
T18	0	3	0	0
T20	0	4	0	0
T23	5357	5	0	0
T24	2386	10	0	0
T25	2614	13	0	0
T105	0	10	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233763711	4210	0	0
T1	133939	51	0	0
T2	0	40	0	0
T4	113502	13	0	0
T5	81632	0	0	0
T6	834	0	0	0
T7	2017	0	0	0
T16	1780	0	0	0
T17	5476	13	0	0
T18	0	1	0	0
T20	0	4	0	0
T23	4354	1	0	0
T24	1275	7	0	0
T25	1423	8	0	0
T105	0	9	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233763711	4780	0	0
T1	133939	58	0	0
T2	0	42	0	0
T4	113502	13	0	0
T5	81632	0	0	0
T6	834	0	0	0
T7	2017	0	0	0
T16	1780	0	0	0
T17	5476	13	0	0
T18	0	3	0	0
T20	0	4	0	0
T23	4354	5	0	0
T24	1275	10	0	0
T25	1423	13	0	0
T105	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T23,T24
1	1	Covered	T4,T23,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	468720624	4301	0	0
g_div2.Div2Whole_A	468720624	5034	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468720624	4301	0	0
T1	267852	51	0	0
T2	0	41	0	0
T4	225832	13	0	0
T5	163385	0	0	0
T6	1706	0	0	0
T7	4059	0	0	0
T16	3624	0	0	0
T17	9787	13	0	0
T18	0	1	0	0
T20	0	4	0	0
T23	5357	1	0	0
T24	2386	7	0	0
T25	2614	10	0	0
T105	0	9	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468720624	5034	0	0
T1	267852	58	0	0
T2	0	43	0	0
T4	225832	13	0	0
T5	163385	0	0	0
T6	1706	0	0	0
T7	4059	0	0	0
T16	3624	0	0	0
T17	9787	14	0	0
T18	0	3	0	0
T20	0	4	0	0
T23	5357	5	0	0
T24	2386	10	0	0
T25	2614	13	0	0
T105	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T23,T24
1	1	Covered	T4,T23,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	233763711	4210	0	0
g_div4.Div4Whole_A	233763711	4780	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233763711	4210	0	0
T1	133939	51	0	0
T2	0	40	0	0
T4	113502	13	0	0
T5	81632	0	0	0
T6	834	0	0	0
T7	2017	0	0	0
T16	1780	0	0	0
T17	5476	13	0	0
T18	0	1	0	0
T20	0	4	0	0
T23	4354	1	0	0
T24	1275	7	0	0
T25	1423	8	0	0
T105	0	9	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233763711	4780	0	0
T1	133939	58	0	0
T2	0	42	0	0
T4	113502	13	0	0
T5	81632	0	0	0
T6	834	0	0	0
T7	2017	0	0	0
T16	1780	0	0	0
T17	5476	13	0	0
T18	0	3	0	0
T20	0	4	0	0
T23	4354	5	0	0
T24	1275	10	0	0
T25	1423	13	0	0
T105	0	10	0	0