Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47141	0	0
CgEnOn_A	2147483647	37655	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47141	0	0
T1	4067968	112	0	0
T2	1777192	0	0	0
T4	854580	86	0	0
T5	1029692	3	0	0
T6	6511	3	0	0
T7	15539	42	0	0
T16	21918	9	0	0
T17	61864	3	0	0
T18	5884	0	0	0
T19	12799	3	0	0
T20	101979	0	0	0
T21	5885	1	0	0
T22	6492	0	0	0
T23	11888	3	0	0
T24	4294	3	0	0
T25	4745	3	0	0
T26	458145	5	0	0
T41	1315	15	0	0
T42	0	20	0	0
T43	0	20	0	0
T148	0	20	0	0
T149	0	15	0	0
T150	0	15	0	0
T151	0	20	0	0
T154	2002	0	0	0
T155	2332	0	0	0
T156	2614	0	0	0
T159	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37655	0	0
T1	4067968	97	0	0
T2	1777192	149	0	0
T3	0	707	0	0
T4	854580	56	0	0
T5	1029692	0	0	0
T6	6511	0	0	0
T7	15539	39	0	0
T16	21918	6	0	0
T17	61864	0	0	0
T18	8258	0	0	0
T19	17938	0	0	0
T20	143376	0	0	0
T21	5885	4	0	0
T22	6492	0	0	0
T26	458145	4	0	0
T38	3256	0	0	0
T41	1315	24	0	0
T42	0	20	0	0
T43	0	20	0	0
T52	0	2	0	0
T108	0	4	0	0
T110	0	4	0	0
T148	0	20	0	0
T149	0	15	0	0
T150	0	15	0	0
T151	0	20	0	0
T152	0	3	0	0
T154	2002	0	0	0
T155	2332	0	0	0
T156	2614	0	0	0
T157	2331	0	0	0
T158	1777	0	0	0
T159	0	4	0	0
T160	0	39	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233763307	153	0	0
CgEnOn_A	233763307	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233763307	153	0	0
T1	133939	1	0	0
T2	394886	0	0	0
T5	81632	0	0	0
T16	1779	0	0	0
T17	5476	0	0	0
T18	676	0	0	0
T19	1434	0	0	0
T20	12077	0	0	0
T21	1296	0	0	0
T22	1422	0	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T159	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233763307	153	0	0
T1	133939	1	0	0
T2	394886	0	0	0
T5	81632	0	0	0
T16	1779	0	0	0
T17	5476	0	0	0
T18	676	0	0	0
T19	1434	0	0	0
T20	12077	0	0	0
T21	1296	0	0	0
T22	1422	0	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	116881047	153	0	0
CgEnOn_A	116881047	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116881047	153	0	0
T1	669688	1	0	0
T2	197442	0	0	0
T5	40816	0	0	0
T16	890	0	0	0
T17	2737	0	0	0
T18	338	0	0	0
T19	717	0	0	0
T20	6037	0	0	0
T21	648	0	0	0
T22	711	0	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T159	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116881047	153	0	0
T1	669688	1	0	0
T2	197442	0	0	0
T5	40816	0	0	0
T16	890	0	0	0
T17	2737	0	0	0
T18	338	0	0	0
T19	717	0	0	0
T20	6037	0	0	0
T21	648	0	0	0
T22	711	0	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468720198	153	0	0
CgEnOn_A	468720198	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468720198	153	0	0
T1	267852	1	0	0
T2	789980	0	0	0
T5	163384	0	0	0
T16	3624	0	0	0
T17	9787	0	0	0
T18	1360	0	0	0
T19	2988	0	0	0
T20	23283	0	0	0
T21	2645	0	0	0
T22	2937	0	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T159	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468720198	144	0	0
T1	267852	1	0	0
T2	789980	0	0	0
T5	163384	0	0	0
T16	3624	0	0	0
T17	9787	0	0	0
T18	1360	0	0	0
T19	2988	0	0	0
T20	23283	0	0	0
T21	2645	0	0	0
T22	2937	0	0	0
T41	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T52	0	2	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T152	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	498457097	135	0	0
CgEnOn_A	498457097	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	135	0	0
T10	105816	1	0	0
T11	179878	0	0	0
T26	458145	0	0	0
T38	3256	0	0	0
T41	1315	2	0	0
T42	0	4	0	0
T43	0	4	0	0
T52	0	2	0	0
T148	0	2	0	0
T149	0	1	0	0
T150	0	4	0	0
T151	0	5	0	0
T152	0	3	0	0
T154	2002	0	0	0
T155	2332	0	0	0
T156	2614	0	0	0
T157	2331	0	0	0
T158	1777	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	133	0	0
T10	105816	0	0	0
T11	179878	0	0	0
T26	458145	0	0	0
T38	3256	0	0	0
T41	1315	2	0	0
T42	0	4	0	0
T43	0	4	0	0
T52	0	2	0	0
T148	0	2	0	0
T149	0	1	0	0
T150	0	4	0	0
T151	0	5	0	0
T152	0	3	0	0
T153	0	3	0	0
T154	2002	0	0	0
T155	2332	0	0	0
T156	2614	0	0	0
T157	2331	0	0	0
T158	1777	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	116881047	153	0	0
CgEnOn_A	116881047	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116881047	153	0	0
T1	669688	1	0	0
T2	197442	0	0	0
T5	40816	0	0	0
T16	890	0	0	0
T17	2737	0	0	0
T18	338	0	0	0
T19	717	0	0	0
T20	6037	0	0	0
T21	648	0	0	0
T22	711	0	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T159	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116881047	153	0	0
T1	669688	1	0	0
T2	197442	0	0	0
T5	40816	0	0	0
T16	890	0	0	0
T17	2737	0	0	0
T18	338	0	0	0
T19	717	0	0	0
T20	6037	0	0	0
T21	648	0	0	0
T22	711	0	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	498457097	135	0	0
CgEnOn_A	498457097	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	135	0	0
T10	105816	1	0	0
T11	179878	0	0	0
T26	458145	0	0	0
T38	3256	0	0	0
T41	1315	2	0	0
T42	0	4	0	0
T43	0	4	0	0
T52	0	2	0	0
T148	0	2	0	0
T149	0	1	0	0
T150	0	4	0	0
T151	0	5	0	0
T152	0	3	0	0
T154	2002	0	0	0
T155	2332	0	0	0
T156	2614	0	0	0
T157	2331	0	0	0
T158	1777	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	133	0	0
T10	105816	0	0	0
T11	179878	0	0	0
T26	458145	0	0	0
T38	3256	0	0	0
T41	1315	2	0	0
T42	0	4	0	0
T43	0	4	0	0
T52	0	2	0	0
T148	0	2	0	0
T149	0	1	0	0
T150	0	4	0	0
T151	0	5	0	0
T152	0	3	0	0
T153	0	3	0	0
T154	2002	0	0	0
T155	2332	0	0	0
T156	2614	0	0	0
T157	2331	0	0	0
T158	1777	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	116881047	153	0	0
CgEnOn_A	116881047	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116881047	153	0	0
T1	669688	1	0	0
T2	197442	0	0	0
T5	40816	0	0	0
T16	890	0	0	0
T17	2737	0	0	0
T18	338	0	0	0
T19	717	0	0	0
T20	6037	0	0	0
T21	648	0	0	0
T22	711	0	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T159	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116881047	153	0	0
T1	669688	1	0	0
T2	197442	0	0	0
T5	40816	0	0	0
T16	890	0	0	0
T17	2737	0	0	0
T18	338	0	0	0
T19	717	0	0	0
T20	6037	0	0	0
T21	648	0	0	0
T22	711	0	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T148	0	4	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233763307	7544	0	0
CgEnOn_A	233763307	5181	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233763307	7544	0	0
T1	133939	24	0	0
T4	113502	22	0	0
T5	81632	1	0	0
T6	834	1	0	0
T7	2017	12	0	0
T16	1779	1	0	0
T17	5476	1	0	0
T23	4354	1	0	0
T24	1274	1	0	0
T25	1422	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233763307	5181	0	0
T1	133939	19	0	0
T2	0	36	0	0
T3	0	230	0	0
T4	113502	12	0	0
T5	81632	0	0	0
T6	834	0	0	0
T7	2017	11	0	0
T16	1779	0	0	0
T17	5476	0	0	0
T18	676	0	0	0
T19	1434	0	0	0
T20	12077	0	0	0
T21	0	1	0	0
T41	0	3	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	116881047	7246	0	0
CgEnOn_A	116881047	4883	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116881047	7246	0	0
T1	669688	21	0	0
T4	56751	22	0	0
T5	40816	1	0	0
T6	417	1	0	0
T7	1008	14	0	0
T16	890	1	0	0
T17	2737	1	0	0
T23	2177	1	0	0
T24	635	1	0	0
T25	709	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116881047	4883	0	0
T1	669688	16	0	0
T2	0	38	0	0
T3	0	235	0	0
T4	56751	12	0	0
T5	40816	0	0	0
T6	417	0	0	0
T7	1008	13	0	0
T16	890	0	0	0
T17	2737	0	0	0
T18	338	0	0	0
T19	717	0	0	0
T20	6037	0	0	0
T21	0	1	0	0
T41	0	3	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468720198	7781	0	0
CgEnOn_A	468720198	5409	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468720198	7781	0	0
T1	267852	24	0	0
T4	225831	23	0	0
T5	163384	1	0	0
T6	1706	1	0	0
T7	4058	16	0	0
T16	3624	1	0	0
T17	9787	1	0	0
T23	5357	1	0	0
T24	2385	1	0	0
T25	2614	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468720198	5409	0	0
T1	267852	19	0	0
T2	0	37	0	0
T3	0	242	0	0
T4	225831	13	0	0
T5	163384	0	0	0
T6	1706	0	0	0
T7	4058	15	0	0
T16	3624	0	0	0
T17	9787	0	0	0
T18	1360	0	0	0
T19	2988	0	0	0
T20	23283	0	0	0
T21	0	1	0	0
T41	0	3	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	239030054	7557	0	0
CgEnOn_A	239030054	5183	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239030054	7557	0	0
T1	141130	22	0	0
T4	118680	21	0	0
T5	81696	1	0	0
T6	853	1	0	0
T7	2029	13	0	0
T16	1812	1	0	0
T17	4893	1	0	0
T23	2678	1	0	0
T24	1193	1	0	0
T25	1307	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239030054	5183	0	0
T1	141130	16	0	0
T2	0	34	0	0
T3	0	236	0	0
T4	118680	11	0	0
T5	81696	0	0	0
T6	853	0	0	0
T7	2029	12	0	0
T16	1812	0	0	0
T17	4893	0	0	0
T18	680	0	0	0
T19	1494	0	0	0
T20	11642	0	0	0
T21	0	1	0	0
T41	0	2	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T16
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	498457097	3979	0	0
CgEnOn_A	498457097	3979	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	3979	0	0
T1	292817	38	0	0
T2	0	38	0	0
T4	229248	19	0	0
T5	188198	0	0	0
T6	1777	0	0	0
T7	4228	0	0	0
T16	3776	6	0	0
T17	10195	0	0	0
T18	1417	0	0	0
T19	3113	3	0	0
T20	24254	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T108	0	1	0	0
T109	0	8	0	0
T110	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	3979	0	0
T1	292817	38	0	0
T2	0	38	0	0
T4	229248	19	0	0
T5	188198	0	0	0
T6	1777	0	0	0
T7	4228	0	0	0
T16	3776	6	0	0
T17	10195	0	0	0
T18	1417	0	0	0
T19	3113	3	0	0
T20	24254	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T108	0	1	0	0
T109	0	8	0	0
T110	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T16
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	498457097	4010	0	0
CgEnOn_A	498457097	4008	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	4010	0	0
T1	292817	38	0	0
T2	0	42	0	0
T4	229248	19	0	0
T5	188198	0	0	0
T6	1777	0	0	0
T7	4228	0	0	0
T16	3776	11	0	0
T17	10195	0	0	0
T18	1417	0	0	0
T19	3113	4	0	0
T20	24254	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T108	0	1	0	0
T109	0	4	0	0
T110	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	4008	0	0
T1	292817	38	0	0
T2	0	42	0	0
T4	229248	19	0	0
T5	188198	0	0	0
T6	1777	0	0	0
T7	4228	0	0	0
T16	3776	11	0	0
T17	10195	0	0	0
T18	1417	0	0	0
T19	3113	4	0	0
T20	24254	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T108	0	1	0	0
T109	0	4	0	0
T110	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T16
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	498457097	3992	0	0
CgEnOn_A	498457097	3993	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	3992	0	0
T1	292817	33	0	0
T2	0	40	0	0
T4	229248	19	0	0
T5	188198	0	0	0
T6	1777	0	0	0
T7	4228	0	0	0
T16	3776	6	0	0
T17	10195	0	0	0
T18	1417	0	0	0
T19	3113	4	0	0
T20	24254	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T108	0	1	0	0
T109	0	6	0	0
T110	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	3993	0	0
T1	292817	33	0	0
T2	0	40	0	0
T4	229248	19	0	0
T5	188198	0	0	0
T6	1777	0	0	0
T7	4228	0	0	0
T16	3776	6	0	0
T17	10195	0	0	0
T18	1417	0	0	0
T19	3113	4	0	0
T20	24254	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T108	0	1	0	0
T109	0	6	0	0
T110	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T16
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	498457097	3997	0	0
CgEnOn_A	498457097	3997	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	3997	0	0
T1	292817	44	0	0
T2	0	36	0	0
T4	229248	19	0	0
T5	188198	0	0	0
T6	1777	0	0	0
T7	4228	0	0	0
T16	3776	7	0	0
T17	10195	0	0	0
T18	1417	0	0	0
T19	3113	4	0	0
T20	24254	0	0	0
T21	0	1	0	0
T22	0	6	0	0
T108	0	1	0	0
T109	0	8	0	0
T110	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498457097	3997	0	0
T1	292817	44	0	0
T2	0	36	0	0
T4	229248	19	0	0
T5	188198	0	0	0
T6	1777	0	0	0
T7	4228	0	0	0
T16	3776	7	0	0
T17	10195	0	0	0
T18	1417	0	0	0
T19	3113	4	0	0
T20	24254	0	0	0
T21	0	1	0	0
T22	0	6	0	0
T108	0	1	0	0
T109	0	8	0	0
T110	0	1	0	0