Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T1
0	1	Covered	T4,T7,T1
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T1
1	0	Covered	T41,T42,T43
1	1	Covered	T4,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1058396236	14132	0	0
GateOpen_A	1058396236	14125	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058396236	14132	0	0
T1	1212610	35	0	0
T2	0	73	0	0
T3	0	618	0	0
T4	514767	37	0	0
T5	367530	0	0	0
T6	3810	0	0	0
T7	9115	30	0	0
T16	8107	0	0	0
T17	22894	0	0	0
T18	3055	0	0	0
T19	6634	0	0	0
T20	53042	0	0	0
T21	0	4	0	0
T41	0	11	0	0
T108	0	4	0	0
T110	0	4	0	0
T160	0	49	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058396236	14125	0	0
T1	1212610	35	0	0
T2	0	73	0	0
T3	0	618	0	0
T4	514767	37	0	0
T5	367530	0	0	0
T6	3810	0	0	0
T7	9115	30	0	0
T16	8107	0	0	0
T17	22894	0	0	0
T18	3055	0	0	0
T19	6634	0	0	0
T20	53042	0	0	0
T21	0	4	0	0
T41	0	11	0	0
T108	0	4	0	0
T110	0	4	0	0
T160	0	49	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T1
0	1	Covered	T4,T7,T1
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T1
1	0	Covered	T41,T42,T43
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	116881445	3469	0	0
GateOpen_A	116881445	3467	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116881445	3469	0	0
T1	669689	8	0	0
T2	0	21	0	0
T3	0	157	0	0
T4	56752	9	0	0
T5	40816	0	0	0
T6	417	0	0	0
T7	1009	7	0	0
T16	890	0	0	0
T17	2737	0	0	0
T18	339	0	0	0
T19	717	0	0	0
T20	6038	0	0	0
T21	0	1	0	0
T41	0	3	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116881445	3467	0	0
T1	669689	8	0	0
T2	0	21	0	0
T3	0	157	0	0
T4	56752	9	0	0
T5	40816	0	0	0
T6	417	0	0	0
T7	1009	7	0	0
T16	890	0	0	0
T17	2737	0	0	0
T18	339	0	0	0
T19	717	0	0	0
T20	6038	0	0	0
T21	0	1	0	0
T41	0	3	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T1
0	1	Covered	T4,T7,T1
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T1
1	0	Covered	T41,T42,T43
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	233763711	3544	0	0
GateOpen_A	233763711	3542	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233763711	3544	0	0
T1	133939	9	0	0
T2	0	19	0	0
T3	0	149	0	0
T4	113502	9	0	0
T5	81632	0	0	0
T6	834	0	0	0
T7	2017	7	0	0
T16	1780	0	0	0
T17	5476	0	0	0
T18	676	0	0	0
T19	1434	0	0	0
T20	12078	0	0	0
T21	0	1	0	0
T41	0	3	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	14	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233763711	3542	0	0
T1	133939	9	0	0
T2	0	19	0	0
T3	0	149	0	0
T4	113502	9	0	0
T5	81632	0	0	0
T6	834	0	0	0
T7	2017	7	0	0
T16	1780	0	0	0
T17	5476	0	0	0
T18	676	0	0	0
T19	1434	0	0	0
T20	12078	0	0	0
T21	0	1	0	0
T41	0	3	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T1
0	1	Covered	T4,T7,T1
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T1
1	0	Covered	T41,T42,T43
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	468720624	3578	0	0
GateOpen_A	468720624	3576	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468720624	3578	0	0
T1	267852	8	0	0
T2	0	18	0	0
T3	0	157	0	0
T4	225832	10	0	0
T5	163385	0	0	0
T6	1706	0	0	0
T7	4059	8	0	0
T16	3624	0	0	0
T17	9787	0	0	0
T18	1360	0	0	0
T19	2989	0	0	0
T20	23284	0	0	0
T21	0	1	0	0
T41	0	3	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468720624	3576	0	0
T1	267852	8	0	0
T2	0	18	0	0
T3	0	157	0	0
T4	225832	10	0	0
T5	163385	0	0	0
T6	1706	0	0	0
T7	4059	8	0	0
T16	3624	0	0	0
T17	9787	0	0	0
T18	1360	0	0	0
T19	2989	0	0	0
T20	23284	0	0	0
T21	0	1	0	0
T41	0	3	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T1
0	1	Covered	T4,T7,T1
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T1
1	0	Covered	T41,T42,T43
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	239030456	3541	0	0
GateOpen_A	239030456	3540	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239030456	3541	0	0
T1	141130	10	0	0
T2	0	15	0	0
T3	0	155	0	0
T4	118681	9	0	0
T5	81697	0	0	0
T6	853	0	0	0
T7	2030	8	0	0
T16	1813	0	0	0
T17	4894	0	0	0
T18	680	0	0	0
T19	1494	0	0	0
T20	11642	0	0	0
T21	0	1	0	0
T41	0	2	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239030456	3540	0	0
T1	141130	10	0	0
T2	0	15	0	0
T3	0	155	0	0
T4	118681	9	0	0
T5	81697	0	0	0
T6	853	0	0	0
T7	2030	8	0	0
T16	1813	0	0	0
T17	4894	0	0	0
T18	680	0	0	0
T19	1494	0	0	0
T20	11642	0	0	0
T21	0	1	0	0
T41	0	2	0	0
T108	0	1	0	0
T110	0	1	0	0
T160	0	11	0	0