Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	641509	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3730395

1

T5

16

T6

11

T7

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1071168	1			T5	16		T6	15		T7	9
values[0x0]	1517941	1			T5	10		T6	20		T7	9
values[0x1]	1782795	1			T5	9		T6	11		T7	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	352485	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4019419

1

T5

17

T6

12

T7

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17292	1			T34	6		T35	2		T47	1
valid_sources[0x01]	16465	1			T34	3		T43	2		T44	2
valid_sources[0x02]	18972	1			T34	6		T68	5		T66	4
valid_sources[0x03]	17072	1			T34	8		T37	7		T48	1
valid_sources[0x04]	18292	1			T34	4		T44	1		T47	2
valid_sources[0x05]	16131	1			T5	1		T37	20		T46	1
valid_sources[0x06]	15820	1			T35	1		T37	34		T44	2
valid_sources[0x07]	15777	1			T34	3		T46	2		T44	7
valid_sources[0x08]	16778	1			T7	3		T34	4		T37	46
valid_sources[0x09]	17770	1			T34	2		T46	9		T47	2
valid_sources[0x0a]	16347	1			T6	3		T34	1		T35	2
valid_sources[0x0b]	17331	1			T34	4		T47	1		T68	25
valid_sources[0x0c]	18204	1			T7	1		T34	2		T35	1
valid_sources[0x0d]	17235	1			T34	3		T35	1		T43	1
valid_sources[0x0e]	16607	1			T34	3		T44	6		T47	1
valid_sources[0x0f]	16433	1			T34	7		T44	7		T47	2
valid_sources[0x10]	16327	1			T34	4		T46	1		T47	2
valid_sources[0x11]	18656	1			T46	6		T44	5		T47	1
valid_sources[0x12]	16780	1			T6	1		T34	4		T37	11
valid_sources[0x13]	17492	1			T7	1		T34	3		T44	4
valid_sources[0x14]	17875	1			T34	6		T46	18		T47	4
valid_sources[0x15]	16545	1			T34	8		T37	42		T44	2
valid_sources[0x16]	18069	1			T5	4		T34	4		T65	12
valid_sources[0x17]	17699	1			T34	2		T47	1		T67	2
valid_sources[0x18]	18027	1			T6	2		T34	5		T37	10
valid_sources[0x19]	15675	1			T34	4		T44	1		T47	2
valid_sources[0x1a]	16538	1			T34	3		T45	4		T48	1
valid_sources[0x1b]	18081	1			T34	1		T37	23		T44	13
valid_sources[0x1c]	17398	1			T34	3		T44	1		T47	3
valid_sources[0x1d]	16099	1			T34	2		T35	2		T44	1
valid_sources[0x1e]	16983	1			T34	2		T47	3		T45	9
valid_sources[0x1f]	17318	1			T5	1		T34	5		T37	10
valid_sources[0x20]	15921	1			T34	7		T46	3		T67	3
valid_sources[0x21]	18180	1			T34	8		T46	12		T44	5
valid_sources[0x22]	17618	1			T34	3		T46	1		T44	3
valid_sources[0x23]	18016	1			T34	6		T65	41		T44	1
valid_sources[0x24]	17844	1			T7	1		T34	7		T37	44
valid_sources[0x25]	16050	1			T7	1		T34	5		T65	22
valid_sources[0x26]	18696	1			T34	3		T35	1		T47	2
valid_sources[0x27]	16247	1			T34	2		T44	1		T47	1
valid_sources[0x28]	16734	1			T34	1		T37	44		T46	3
valid_sources[0x29]	17446	1			T6	1		T34	2		T47	3
valid_sources[0x2a]	16577	1			T7	2		T34	6		T65	11
valid_sources[0x2b]	16052	1			T5	2		T34	6		T37	19
valid_sources[0x2c]	17080	1			T34	4		T44	4		T47	2
valid_sources[0x2d]	17064	1			T7	1		T34	3		T66	1
valid_sources[0x2e]	17840	1			T34	4		T44	1		T47	3
valid_sources[0x2f]	16583	1			T34	2		T35	1		T36	13
valid_sources[0x30]	20592	1			T34	4		T35	1		T46	4
valid_sources[0x31]	17396	1			T34	3		T35	2		T48	3
valid_sources[0x32]	17811	1			T34	1		T47	2		T45	2
valid_sources[0x33]	18188	1			T6	3		T34	6		T44	2
valid_sources[0x34]	17429	1			T34	3		T47	2		T66	1
valid_sources[0x35]	16704	1			T35	1		T43	1		T44	1
valid_sources[0x36]	17050	1			T34	3		T35	1		T45	13
valid_sources[0x37]	16115	1			T34	1		T68	5		T66	1
valid_sources[0x38]	17069	1			T34	6		T35	1		T44	4
valid_sources[0x39]	15962	1			T34	8		T35	1		T46	12
valid_sources[0x3a]	15492	1			T6	1		T34	6		T35	2
valid_sources[0x3b]	17006	1			T34	6		T37	25		T47	1
valid_sources[0x3c]	16539	1			T34	2		T35	1		T47	1
valid_sources[0x3d]	16036	1			T34	7		T46	1		T47	2
valid_sources[0x3e]	18955	1			T6	2		T34	3		T44	4
valid_sources[0x3f]	16292	1			T34	3		T37	20		T47	1
valid_sources[0x40]	16821	1			T5	2		T34	2		T35	1
valid_sources[0x41]	15940	1			T34	5		T35	1		T47	3
valid_sources[0x42]	17220	1			T35	2		T44	2		T48	1
valid_sources[0x43]	16697	1			T34	2		T46	6		T65	50
valid_sources[0x44]	16639	1			T6	1		T34	1		T46	3
valid_sources[0x45]	17300	1			T34	7		T65	25		T44	4
valid_sources[0x46]	16868	1			T34	4		T65	21		T44	2
valid_sources[0x47]	17426	1			T6	2		T34	3		T47	2
valid_sources[0x48]	16541	1			T34	4		T46	4		T44	5
valid_sources[0x49]	15748	1			T34	1		T35	1		T37	23
valid_sources[0x4a]	17363	1			T34	5		T37	24		T44	2
valid_sources[0x4b]	18019	1			T34	8		T68	3		T90	1
valid_sources[0x4c]	16267	1			T6	2		T34	6		T35	1
valid_sources[0x4d]	16862	1			T34	1		T46	3		T47	1
valid_sources[0x4e]	16585	1			T34	1		T47	3		T68	34
valid_sources[0x4f]	17772	1			T34	7		T35	2		T37	24
valid_sources[0x50]	17493	1			T34	5		T47	1		T67	6
valid_sources[0x51]	16558	1			T7	1		T34	4		T43	1
valid_sources[0x52]	17844	1			T34	4		T37	25		T44	3
valid_sources[0x53]	18040	1			T34	2		T47	1		T66	1
valid_sources[0x54]	21151	1			T34	11		T47	2		T66	6
valid_sources[0x55]	16475	1			T7	1		T34	3		T35	1
valid_sources[0x56]	16748	1			T34	5		T47	1		T45	17
valid_sources[0x57]	16035	1			T34	7		T46	1		T44	4
valid_sources[0x58]	17077	1			T34	6		T35	1		T47	2
valid_sources[0x59]	15523	1			T34	4		T47	3		T45	8
valid_sources[0x5a]	16421	1			T34	3		T37	35		T43	1
valid_sources[0x5b]	17747	1			T34	3		T45	11		T66	7
valid_sources[0x5c]	16322	1			T34	1		T35	1		T46	3
valid_sources[0x5d]	16424	1			T34	9		T45	9		T48	4
valid_sources[0x5e]	17563	1			T34	6		T80	7		T75	9
valid_sources[0x5f]	16170	1			T7	1		T34	1		T44	2
valid_sources[0x60]	17657	1			T34	1		T44	1		T45	8
valid_sources[0x61]	18152	1			T34	5		T44	2		T47	2
valid_sources[0x62]	16791	1			T6	1		T34	6		T46	5
valid_sources[0x63]	16944	1			T6	3		T43	1		T47	4
valid_sources[0x64]	16599	1			T34	1		T35	2		T47	2
valid_sources[0x65]	17135	1			T5	1		T7	1		T34	1
valid_sources[0x66]	17507	1			T34	2		T37	7		T68	7
valid_sources[0x67]	16011	1			T34	2		T47	1		T48	1
valid_sources[0x68]	17117	1			T5	2		T6	2		T34	1
valid_sources[0x69]	16493	1			T34	7		T47	2		T48	4
valid_sources[0x6a]	16031	1			T34	2		T35	1		T36	7
valid_sources[0x6b]	17007	1			T7	1		T34	2		T44	1
valid_sources[0x6c]	16847	1			T6	7		T34	4		T35	1
valid_sources[0x6d]	16702	1			T34	1		T35	2		T45	3
valid_sources[0x6e]	17325	1			T34	10		T45	1		T66	3
valid_sources[0x6f]	17336	1			T34	4		T37	23		T47	1
valid_sources[0x70]	16872	1			T34	2		T36	13		T46	2
valid_sources[0x71]	15959	1			T34	5		T47	3		T45	1
valid_sources[0x72]	17659	1			T34	1		T35	1		T44	14
valid_sources[0x73]	17009	1			T34	2		T37	25		T47	3
valid_sources[0x74]	16803	1			T34	4		T35	1		T47	4
valid_sources[0x75]	15385	1			T34	4		T35	1		T37	20
valid_sources[0x76]	17080	1			T34	2		T35	1		T46	3
valid_sources[0x77]	17862	1			T6	2		T34	2		T43	1
valid_sources[0x78]	16840	1			T34	2		T44	2		T47	1
valid_sources[0x79]	17264	1			T34	4		T35	1		T46	6
valid_sources[0x7a]	17400	1			T34	3		T47	1		T45	7
valid_sources[0x7b]	16858	1			T34	9		T47	1		T45	8
valid_sources[0x7c]	16859	1			T34	4		T35	2		T46	2
valid_sources[0x7d]	16077	1			T34	3		T47	1		T68	4
valid_sources[0x7e]	16829	1			T34	5		T43	1		T44	1
valid_sources[0x7f]	17534	1			T34	2		T35	1		T43	1
valid_sources[0x80]	17592	1			T34	1		T35	1		T68	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

939546

1

T5

11

T6

6

T7

2

values[0x0]

all_enables

biggest_size

1419829

1

T5

3

T6

4

T7

2

values[0x1]

all_enables

biggest_size

1371020

1

T5

2

T6

1

T7

1