Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	849556290	77679	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	849556290	77679	0	0
T1	4584610	405	0	0
T2	225345	196	0	0
T3	2199240	1945	0	0
T4	573255	0	0	0
T8	369095	0	0	0
T11	385940	56	0	0
T12	0	280	0	0
T13	0	479	0	0
T14	0	77	0	0
T15	0	298	0	0
T16	0	323	0	0
T17	0	116	0	0
T18	5595	0	0	0
T19	4960	0	0	0
T20	4540	0	0	0
T21	9475	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169911258	11355	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	11355	0	0
T1	916922	52	0	0
T2	45069	33	0	0
T3	439848	292	0	0
T4	114651	0	0	0
T8	73819	0	0	0
T11	77188	9	0	0
T12	0	37	0	0
T13	0	62	0	0
T14	0	11	0	0
T15	0	41	0	0
T16	0	47	0	0
T17	0	15	0	0
T18	1119	0	0	0
T19	992	0	0	0
T20	908	0	0	0
T21	1895	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169911258	15612	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	15612	0	0
T1	916922	80	0	0
T2	45069	41	0	0
T3	439848	387	0	0
T4	114651	0	0	0
T8	73819	0	0	0
T11	77188	11	0	0
T12	0	58	0	0
T13	0	99	0	0
T14	0	15	0	0
T15	0	57	0	0
T16	0	65	0	0
T17	0	24	0	0
T18	1119	0	0	0
T19	992	0	0	0
T20	908	0	0	0
T21	1895	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169911258	23801	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	23801	0	0
T1	916922	132	0	0
T2	45069	52	0	0
T3	439848	585	0	0
T4	114651	0	0	0
T8	73819	0	0	0
T11	77188	16	0	0
T12	0	94	0	0
T13	0	160	0	0
T14	0	23	0	0
T15	0	97	0	0
T16	0	105	0	0
T17	0	38	0	0
T18	1119	0	0	0
T19	992	0	0	0
T20	908	0	0	0
T21	1895	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169911258	11273	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	11273	0	0
T1	916922	59	0	0
T2	45069	30	0	0
T3	439848	291	0	0
T4	114651	0	0	0
T8	73819	0	0	0
T11	77188	9	0	0
T12	0	36	0	0
T13	0	61	0	0
T14	0	11	0	0
T15	0	39	0	0
T16	0	41	0	0
T17	0	15	0	0
T18	1119	0	0	0
T19	992	0	0	0
T20	908	0	0	0
T21	1895	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169911258	15638	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	15638	0	0
T1	916922	82	0	0
T2	45069	40	0	0
T3	439848	390	0	0
T4	114651	0	0	0
T8	73819	0	0	0
T11	77188	11	0	0
T12	0	55	0	0
T13	0	97	0	0
T14	0	17	0	0
T15	0	64	0	0
T16	0	65	0	0
T17	0	24	0	0
T18	1119	0	0	0
T19	992	0	0	0
T20	908	0	0	0
T21	1895	0	0	0