Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	169911258	167443887	0	0
AllClkBypReqTrue_A	169911258	142960	0	0
IoClkBypReqFalse_A	169911258	167357369	0	2409
IoClkBypReqTrue_A	169911258	224652	0	0
LcClkBypAckFalse_A	169911258	167455171	0	0
LcClkBypAckTrue_A	169911258	131676	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	167443887	0	0
T1	916922	895670	0	0
T2	45069	45019	0	0
T4	114651	11596	0	0
T5	2237	1910	0	0
T6	1545	1331	0	0
T7	1335	1307	0	0
T22	991	893	0	0
T23	929	865	0	0
T24	2187	2014	0	0
T25	1527	1482	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	142960	0	0
T1	916922	762	0	0
T2	45069	0	0	0
T3	0	2228	0	0
T4	114651	0	0	0
T5	2237	157	0	0
T6	1545	174	0	0
T7	1335	0	0	0
T11	0	428	0	0
T22	991	73	0	0
T23	929	0	0	0
T24	2187	157	0	0
T25	1527	0	0	0
T101	0	265	0	0
T102	0	252	0	0
T103	0	51	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	167357369	0	2409
T1	916922	894864	0	3
T2	45069	45017	0	3
T4	114651	11556	0	3
T5	2237	1863	0	3
T6	1545	1468	0	3
T7	1335	1144	0	3
T22	991	894	0	3
T23	929	863	0	3
T24	2187	1761	0	3
T25	1527	1480	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	224652	0	0
T1	916922	1556	0	0
T2	45069	0	0	0
T3	0	3592	0	0
T4	114651	0	0	0
T5	2237	202	0	0
T6	1545	35	0	0
T7	1335	161	0	0
T11	0	798	0	0
T22	991	70	0	0
T23	929	0	0	0
T24	2187	408	0	0
T25	1527	0	0	0
T101	0	529	0	0
T104	0	30	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	167455171	0	0
T1	916922	895515	0	0
T2	45069	45019	0	0
T4	114651	11596	0	0
T5	2237	1940	0	0
T6	1545	1475	0	0
T7	1335	1261	0	0
T22	991	923	0	0
T23	929	865	0	0
T24	2187	1934	0	0
T25	1527	1482	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169911258	131676	0	0
T1	916922	917	0	0
T2	45069	0	0	0
T3	0	2174	0	0
T4	114651	0	0	0
T5	2237	127	0	0
T6	1545	30	0	0
T7	1335	46	0	0
T11	0	566	0	0
T22	991	43	0	0
T23	929	0	0	0
T24	2187	237	0	0
T25	1527	0	0	0
T101	0	266	0	0
T104	0	26	0	0