Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16593	0	0
TransStop_A	2147483647	8503	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16593	0	0
T1	3619692	115	0	0
T2	667688	0	0	0
T3	3844928	728	0	0
T4	487864	0	0	0
T8	295280	0	0	0
T11	1187028	35	0	0
T14	0	158	0	0
T18	8444	0	0	0
T19	15568	0	0	0
T20	34288	0	0	0
T21	7900	13	0	0
T105	0	20	0	0
T106	0	39	0	0
T107	0	4	0	0
T108	0	4	0	0
T109	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8503	0	0
T1	3619692	56	0	0
T2	667688	0	0	0
T3	3844928	391	0	0
T4	487864	0	0	0
T8	295280	0	0	0
T11	1187028	20	0	0
T14	0	85	0	0
T18	8444	0	0	0
T19	15568	0	0	0
T20	34288	0	0	0
T21	7900	8	0	0
T105	0	5	0	0
T106	0	23	0	0
T107	0	4	0	0
T108	0	4	0	0
T109	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	558008925	4160	0	0
TransStop_A	558008925	2129	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008925	4160	0	0
T1	904923	28	0	0
T2	166922	0	0	0
T3	961232	177	0	0
T4	121966	0	0	0
T8	73820	0	0	0
T11	296757	11	0	0
T14	0	36	0	0
T18	2111	0	0	0
T19	3892	0	0	0
T20	8572	0	0	0
T21	1975	4	0	0
T105	0	5	0	0
T106	0	10	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008925	2129	0	0
T1	904923	14	0	0
T2	166922	0	0	0
T3	961232	92	0	0
T4	121966	0	0	0
T8	73820	0	0	0
T11	296757	5	0	0
T14	0	22	0	0
T18	2111	0	0	0
T19	3892	0	0	0
T20	8572	0	0	0
T21	1975	2	0	0
T105	0	1	0	0
T106	0	5	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	558008925	4158	0	0
TransStop_A	558008925	2126	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008925	4158	0	0
T1	904923	30	0	0
T2	166922	0	0	0
T3	961232	181	0	0
T4	121966	0	0	0
T8	73820	0	0	0
T11	296757	10	0	0
T14	0	45	0	0
T18	2111	0	0	0
T19	3892	0	0	0
T20	8572	0	0	0
T21	1975	3	0	0
T105	0	6	0	0
T106	0	11	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008925	2126	0	0
T1	904923	17	0	0
T2	166922	0	0	0
T3	961232	100	0	0
T4	121966	0	0	0
T8	73820	0	0	0
T11	296757	6	0	0
T14	0	24	0	0
T18	2111	0	0	0
T19	3892	0	0	0
T20	8572	0	0	0
T21	1975	2	0	0
T105	0	1	0	0
T106	0	7	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	558008925	4199	0	0
TransStop_A	558008925	2159	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008925	4199	0	0
T1	904923	31	0	0
T2	166922	0	0	0
T3	961232	206	0	0
T4	121966	0	0	0
T8	73820	0	0	0
T11	296757	9	0	0
T14	0	42	0	0
T18	2111	0	0	0
T19	3892	0	0	0
T20	8572	0	0	0
T21	1975	4	0	0
T105	0	3	0	0
T106	0	8	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008925	2159	0	0
T1	904923	13	0	0
T2	166922	0	0	0
T3	961232	109	0	0
T4	121966	0	0	0
T8	73820	0	0	0
T11	296757	5	0	0
T14	0	22	0	0
T18	2111	0	0	0
T19	3892	0	0	0
T20	8572	0	0	0
T21	1975	3	0	0
T105	0	1	0	0
T106	0	5	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	558008925	4076	0	0
TransStop_A	558008925	2089	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008925	4076	0	0
T1	904923	26	0	0
T2	166922	0	0	0
T3	961232	164	0	0
T4	121966	0	0	0
T8	73820	0	0	0
T11	296757	5	0	0
T14	0	35	0	0
T18	2111	0	0	0
T19	3892	0	0	0
T20	8572	0	0	0
T21	1975	2	0	0
T105	0	6	0	0
T106	0	10	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008925	2089	0	0
T1	904923	12	0	0
T2	166922	0	0	0
T3	961232	90	0	0
T4	121966	0	0	0
T8	73820	0	0	0
T11	296757	4	0	0
T14	0	17	0	0
T18	2111	0	0	0
T19	3892	0	0	0
T20	8572	0	0	0
T21	1975	1	0	0
T105	0	2	0	0
T106	0	6	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0