Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	170842300	5455776	0	0
clk_enables_rd_A	170842300	52129	0	0
clk_hints_rd_A	170842300	45201	0	0
extclk_ctrl_rd_A	170842300	59534	0	0
extclk_ctrl_regwen_rd_A	170842300	43858	0	0
jitter_enable_rd_A	170842300	64084	0	0
jitter_regwen_rd_A	170842300	49399	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170842300	5455776	0	0
T34	4296	3	0	0
T44	2097	157	0	0
T45	7594	6	0	0
T46	2473	270	0	0
T66	13427	730	0	0
T67	954	2	0	0
T68	9100	5	0	0
T75	2299	35	0	0
T76	10299	440	0	0
T80	21864	0	0	0
T84	0	42	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170842300	52129	0	0
T43	1237	3	0	0
T45	7594	27	0	0
T48	2434	31	0	0
T66	13427	10	0	0
T67	954	0	0	0
T70	7368	17	0	0
T73	0	46	0	0
T75	2299	2	0	0
T76	0	23	0	0
T80	21864	0	0	0
T84	0	17	0	0
T86	729	0	0	0
T90	1101	15	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170842300	45201	0	0
T43	1237	1	0	0
T45	7594	54	0	0
T48	2434	37	0	0
T66	13427	10	0	0
T67	954	0	0	0
T70	7368	32	0	0
T73	0	43	0	0
T75	2299	0	0	0
T76	0	17	0	0
T80	21864	0	0	0
T84	0	19	0	0
T86	729	0	0	0
T87	0	119	0	0
T90	1101	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170842300	59534	0	0
T5	2237	24	0	0
T6	1545	0	0	0
T7	1335	0	0	0
T48	2434	58	0	0
T66	13427	32	0	0
T67	954	0	0	0
T70	7368	26	0	0
T73	0	28	0	0
T75	2299	10	0	0
T76	0	11	0	0
T80	21864	0	0	0
T84	0	14	0	0
T86	729	0	0	0
T87	0	139	0	0
T88	0	35	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170842300	43858	0	0
T43	1237	3	0	0
T45	7594	22	0	0
T48	2434	4	0	0
T66	13427	23	0	0
T67	954	0	0	0
T70	7368	37	0	0
T73	0	36	0	0
T75	2299	0	0	0
T76	0	12	0	0
T80	21864	0	0	0
T84	0	13	0	0
T86	729	0	0	0
T87	0	137	0	0
T90	1101	2	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170842300	64084	0	0
T45	7594	16	0	0
T48	2434	9	0	0
T66	13427	15	0	0
T67	954	0	0	0
T70	7368	28	0	0
T73	0	34	0	0
T75	2299	0	0	0
T76	10299	11	0	0
T80	21864	0	0	0
T84	0	13	0	0
T86	729	0	0	0
T87	0	121	0	0
T88	0	96	0	0
T90	1101	1	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170842300	49399	0	0
T45	7594	19	0	0
T48	2434	10	0	0
T66	13427	6	0	0
T67	954	0	0	0
T70	7368	26	0	0
T73	0	36	0	0
T75	2299	4	0	0
T76	10299	15	0	0
T80	21864	0	0	0
T84	0	24	0	0
T86	729	0	0	0
T87	0	109	0	0
T90	1101	5	0	0