Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	524567662	4788	0	0
g_div2.Div2Whole_A	524567662	5658	0	0
g_div4.Div4Stepped_A	264110183	4679	0	0
g_div4.Div4Whole_A	264110183	5361	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524567662	4788	0	0
T1	851418	31	0	0
T2	160241	0	0	0
T3	0	92	0	0
T4	117084	0	0	0
T5	2148	5	0	0
T6	5935	6	0	0
T7	5131	3	0	0
T11	0	22	0	0
T22	3810	2	0	0
T23	3571	0	0	0
T24	19084	11	0	0
T25	6112	0	0	0
T101	0	14	0	0
T104	0	1	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524567662	5658	0	0
T1	851418	48	0	0
T2	160241	0	0	0
T3	0	119	0	0
T4	117084	0	0	0
T5	2148	5	0	0
T6	5935	6	0	0
T7	5131	5	0	0
T11	0	22	0	0
T22	3810	3	0	0
T23	3571	0	0	0
T24	19084	11	0	0
T25	6112	0	0	0
T101	0	14	0	0
T104	0	1	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264110183	4679	0	0
T1	420604	30	0	0
T2	80053	0	0	0
T3	0	91	0	0
T4	33307	0	0	0
T5	1125	5	0	0
T6	3180	6	0	0
T7	2651	3	0	0
T11	0	22	0	0
T22	1956	2	0	0
T23	1733	0	0	0
T24	10992	11	0	0
T25	3030	0	0	0
T101	0	14	0	0
T104	0	1	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264110183	5361	0	0
T1	420604	40	0	0
T2	80053	0	0	0
T3	0	119	0	0
T4	33307	0	0	0
T5	1125	5	0	0
T6	3180	6	0	0
T7	2651	5	0	0
T11	0	22	0	0
T22	1956	2	0	0
T23	1733	0	0	0
T24	10992	11	0	0
T25	3030	0	0	0
T101	0	14	0	0
T104	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	524567662	4788	0	0
g_div2.Div2Whole_A	524567662	5658	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524567662	4788	0	0
T1	851418	31	0	0
T2	160241	0	0	0
T3	0	92	0	0
T4	117084	0	0	0
T5	2148	5	0	0
T6	5935	6	0	0
T7	5131	3	0	0
T11	0	22	0	0
T22	3810	2	0	0
T23	3571	0	0	0
T24	19084	11	0	0
T25	6112	0	0	0
T101	0	14	0	0
T104	0	1	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524567662	5658	0	0
T1	851418	48	0	0
T2	160241	0	0	0
T3	0	119	0	0
T4	117084	0	0	0
T5	2148	5	0	0
T6	5935	6	0	0
T7	5131	5	0	0
T11	0	22	0	0
T22	3810	3	0	0
T23	3571	0	0	0
T24	19084	11	0	0
T25	6112	0	0	0
T101	0	14	0	0
T104	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	264110183	4679	0	0
g_div4.Div4Whole_A	264110183	5361	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264110183	4679	0	0
T1	420604	30	0	0
T2	80053	0	0	0
T3	0	91	0	0
T4	33307	0	0	0
T5	1125	5	0	0
T6	3180	6	0	0
T7	2651	3	0	0
T11	0	22	0	0
T22	1956	2	0	0
T23	1733	0	0	0
T24	10992	11	0	0
T25	3030	0	0	0
T101	0	14	0	0
T104	0	1	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264110183	5361	0	0
T1	420604	40	0	0
T2	80053	0	0	0
T3	0	119	0	0
T4	33307	0	0	0
T5	1125	5	0	0
T6	3180	6	0	0
T7	2651	5	0	0
T11	0	22	0	0
T22	1956	2	0	0
T23	1733	0	0	0
T24	10992	11	0	0
T25	3030	0	0	0
T101	0	14	0	0
T104	0	1	0	0