Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48828	0	0
CgEnOn_A	2147483647	39173	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48828	0	0
T1	5539256	170	0	0
T2	1028130	3	0	0
T3	7764057	177	0	0
T4	713453	60	0	0
T5	4908	3	0	0
T6	13670	3	0	0
T7	11672	3	0	0
T8	560855	0	0	0
T11	2385499	0	0	0
T18	16939	12	0	0
T19	31149	18	0	0
T20	71571	25	0	0
T21	15980	0	0	0
T22	8646	3	0	0
T23	7954	16	0	0
T24	45112	3	0	0
T25	13710	3	0	0
T28	241828	0	0	0
T131	5620	24	0	0
T132	15163	20	0	0
T133	0	5	0	0
T134	0	15	0	0
T135	0	10	0	0
T136	0	5	0	0
T137	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39173	0	0
T1	5539256	282	0	0
T2	1028130	0	0	0
T3	9778790	1249	0	0
T4	713453	0	0	0
T8	560855	0	0	0
T11	2992203	84	0	0
T18	21221	29	0	0
T19	38934	45	0	0
T20	71571	65	0	0
T21	15980	13	0	0
T23	7954	17	0	0
T24	45112	0	0	0
T25	13710	0	0	0
T28	241828	0	0	0
T105	0	20	0	0
T131	5620	62	0	0
T132	15163	59	0	0
T133	0	9	0	0
T134	0	29	0	0
T135	0	14	0	0
T136	0	7	0	0
T137	0	20	0	0
T138	0	2	0	0
T139	0	32	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	264109765	130	0	0
CgEnOn_A	264109765	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264109765	130	0	0
T3	443621	0	0	0
T8	18828	0	0	0
T11	134949	0	0	0
T18	938	2	0	0
T19	1718	3	0	0
T20	4468	4	0	0
T21	894	0	0	0
T28	23731	0	0	0
T131	622	4	0	0
T132	1707	3	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264109765	130	0	0
T3	443621	0	0	0
T8	18828	0	0	0
T11	134949	0	0	0
T18	938	2	0	0
T19	1718	3	0	0
T20	4468	4	0	0
T21	894	0	0	0
T28	23731	0	0	0
T131	622	4	0	0
T132	1707	3	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	132054202	130	0	0
CgEnOn_A	132054202	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132054202	130	0	0
T3	221809	0	0	0
T8	9416	0	0	0
T11	67472	0	0	0
T18	469	2	0	0
T19	859	3	0	0
T20	2234	4	0	0
T21	447	0	0	0
T28	11865	0	0	0
T131	311	4	0	0
T132	853	3	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132054202	130	0	0
T3	221809	0	0	0
T8	9416	0	0	0
T11	67472	0	0	0
T18	469	2	0	0
T19	859	3	0	0
T20	2234	4	0	0
T21	447	0	0	0
T28	11865	0	0	0
T131	311	4	0	0
T132	853	3	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524567216	130	0	0
CgEnOn_A	524567216	123	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524567216	130	0	0
T3	887617	0	0	0
T8	70865	0	0	0
T11	267598	0	0	0
T18	1928	2	0	0
T19	3502	3	0	0
T20	8975	4	0	0
T21	1895	0	0	0
T28	47514	0	0	0
T131	1309	4	0	0
T132	3493	3	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524567216	123	0	0
T3	887617	0	0	0
T8	70865	0	0	0
T11	267598	0	0	0
T18	1928	2	0	0
T19	3502	3	0	0
T20	8975	4	0	0
T21	1895	0	0	0
T28	47514	0	0	0
T131	1309	4	0	0
T132	3493	3	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558008491	130	0	0
CgEnOn_A	558008491	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	130	0	0
T3	961232	0	0	0
T8	73819	0	0	0
T11	296756	0	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	0	0	0
T28	67494	0	0	0
T131	1378	4	0	0
T132	3702	5	0	0
T133	0	2	0	0
T134	0	7	0	0
T135	0	2	0	0
T136	0	1	0	0
T138	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	127	0	0
T3	961232	0	0	0
T8	73819	0	0	0
T11	296756	0	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	0	0	0
T28	67494	0	0	0
T131	1378	4	0	0
T132	3702	5	0	0
T133	0	2	0	0
T134	0	7	0	0
T135	0	2	0	0
T136	0	1	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	132054202	130	0	0
CgEnOn_A	132054202	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132054202	130	0	0
T3	221809	0	0	0
T8	9416	0	0	0
T11	67472	0	0	0
T18	469	2	0	0
T19	859	3	0	0
T20	2234	4	0	0
T21	447	0	0	0
T28	11865	0	0	0
T131	311	4	0	0
T132	853	3	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132054202	130	0	0
T3	221809	0	0	0
T8	9416	0	0	0
T11	67472	0	0	0
T18	469	2	0	0
T19	859	3	0	0
T20	2234	4	0	0
T21	447	0	0	0
T28	11865	0	0	0
T131	311	4	0	0
T132	853	3	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558008491	130	0	0
CgEnOn_A	558008491	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	130	0	0
T3	961232	0	0	0
T8	73819	0	0	0
T11	296756	0	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	0	0	0
T28	67494	0	0	0
T131	1378	4	0	0
T132	3702	5	0	0
T133	0	2	0	0
T134	0	7	0	0
T135	0	2	0	0
T136	0	1	0	0
T138	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	127	0	0
T3	961232	0	0	0
T8	73819	0	0	0
T11	296756	0	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	0	0	0
T28	67494	0	0	0
T131	1378	4	0	0
T132	3702	5	0	0
T133	0	2	0	0
T134	0	7	0	0
T135	0	2	0	0
T136	0	1	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	132054202	130	0	0
CgEnOn_A	132054202	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132054202	130	0	0
T3	221809	0	0	0
T8	9416	0	0	0
T11	67472	0	0	0
T18	469	2	0	0
T19	859	3	0	0
T20	2234	4	0	0
T21	447	0	0	0
T28	11865	0	0	0
T131	311	4	0	0
T132	853	3	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132054202	130	0	0
T3	221809	0	0	0
T8	9416	0	0	0
T11	67472	0	0	0
T18	469	2	0	0
T19	859	3	0	0
T20	2234	4	0	0
T21	447	0	0	0
T28	11865	0	0	0
T131	311	4	0	0
T132	853	3	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	1	0	0
T137	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	264109765	7762	0	0
CgEnOn_A	264109765	5356	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264109765	7762	0	0
T1	420603	53	0	0
T2	80053	1	0	0
T4	33307	20	0	0
T5	1125	1	0	0
T6	3179	1	0	0
T7	2651	1	0	0
T22	1956	1	0	0
T23	1732	5	0	0
T24	10992	1	0	0
T25	3029	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264109765	5356	0	0
T1	420603	47	0	0
T2	80053	0	0	0
T3	443621	135	0	0
T4	33307	0	0	0
T11	134949	12	0	0
T18	938	2	0	0
T19	1718	3	0	0
T20	0	4	0	0
T23	1732	4	0	0
T24	10992	0	0	0
T25	3029	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T139	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	132054202	7389	0	0
CgEnOn_A	132054202	4986	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132054202	7389	0	0
T1	210297	40	0	0
T2	40026	1	0	0
T4	16654	20	0	0
T5	561	1	0	0
T6	1589	1	0	0
T7	1325	1	0	0
T22	977	1	0	0
T23	866	6	0	0
T24	5494	1	0	0
T25	1515	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132054202	4986	0	0
T1	210297	34	0	0
T2	40026	0	0	0
T3	221809	115	0	0
T4	16654	0	0	0
T11	67472	12	0	0
T18	469	2	0	0
T19	859	3	0	0
T20	0	4	0	0
T23	866	5	0	0
T24	5494	0	0	0
T25	1515	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T139	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	524567216	7911	0	0
CgEnOn_A	524567216	5498	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524567216	7911	0	0
T1	851418	49	0	0
T2	160240	1	0	0
T4	117084	20	0	0
T5	2148	1	0	0
T6	5935	1	0	0
T7	5131	1	0	0
T22	3809	1	0	0
T23	3571	5	0	0
T24	19084	1	0	0
T25	6111	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524567216	5498	0	0
T1	851418	43	0	0
T2	160240	0	0	0
T3	887617	136	0	0
T4	117084	0	0	0
T11	267598	12	0	0
T18	1928	2	0	0
T19	3502	3	0	0
T20	0	4	0	0
T23	3571	4	0	0
T24	19084	0	0	0
T25	6111	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T139	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	267893053	7743	0	0
CgEnOn_A	267893053	5331	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267893053	7743	0	0
T1	437250	49	0	0
T2	80123	1	0	0
T4	58544	20	0	0
T5	1074	1	0	0
T6	2967	1	0	0
T7	2565	1	0	0
T22	1904	1	0	0
T23	1785	5	0	0
T24	9542	1	0	0
T25	3055	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267893053	5331	0	0
T1	437250	43	0	0
T2	80123	0	0	0
T3	461686	135	0	0
T4	58544	0	0	0
T11	136685	13	0	0
T18	947	1	0	0
T19	1706	3	0	0
T20	0	3	0	0
T23	1785	4	0	0
T24	9542	0	0	0
T25	3055	0	0	0
T131	0	6	0	0
T132	0	5	0	0
T139	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Covered	T1,T3,T11
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558008491	4290	0	0
CgEnOn_A	558008491	4288	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	4290	0	0
T1	904922	28	0	0
T2	166922	0	0	0
T3	961232	177	0	0
T4	121966	0	0	0
T8	73819	0	0	0
T11	296756	11	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	4	0	0
T105	0	5	0	0
T131	0	4	0	0
T132	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	4288	0	0
T1	904922	28	0	0
T2	166922	0	0	0
T3	961232	177	0	0
T4	121966	0	0	0
T8	73819	0	0	0
T11	296756	11	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	4	0	0
T105	0	5	0	0
T131	0	4	0	0
T132	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Covered	T1,T3,T11
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558008491	4288	0	0
CgEnOn_A	558008491	4286	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	4288	0	0
T1	904922	30	0	0
T2	166922	0	0	0
T3	961232	181	0	0
T4	121966	0	0	0
T8	73819	0	0	0
T11	296756	10	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	3	0	0
T105	0	6	0	0
T131	0	4	0	0
T132	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	4286	0	0
T1	904922	30	0	0
T2	166922	0	0	0
T3	961232	181	0	0
T4	121966	0	0	0
T8	73819	0	0	0
T11	296756	10	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	3	0	0
T105	0	6	0	0
T131	0	4	0	0
T132	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Covered	T1,T3,T11
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558008491	4329	0	0
CgEnOn_A	558008491	4327	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	4329	0	0
T1	904922	31	0	0
T2	166922	0	0	0
T3	961232	206	0	0
T4	121966	0	0	0
T8	73819	0	0	0
T11	296756	9	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	4	0	0
T105	0	3	0	0
T131	0	4	0	0
T132	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	4327	0	0
T1	904922	31	0	0
T2	166922	0	0	0
T3	961232	206	0	0
T4	121966	0	0	0
T8	73819	0	0	0
T11	296756	9	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	4	0	0
T105	0	3	0	0
T131	0	4	0	0
T132	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T18
1	0	Covered	T1,T3,T11
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	558008491	4206	0	0
CgEnOn_A	558008491	4204	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	4206	0	0
T1	904922	26	0	0
T2	166922	0	0	0
T3	961232	164	0	0
T4	121966	0	0	0
T8	73819	0	0	0
T11	296756	5	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	2	0	0
T105	0	6	0	0
T131	0	4	0	0
T132	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558008491	4204	0	0
T1	904922	26	0	0
T2	166922	0	0	0
T3	961232	164	0	0
T4	121966	0	0	0
T8	73819	0	0	0
T11	296756	5	0	0
T18	2111	2	0	0
T19	3892	3	0	0
T20	8571	5	0	0
T21	1975	2	0	0
T105	0	6	0	0
T131	0	4	0	0
T132	0	5	0	0