Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T23,T1,T18
0	1	Covered	T23,T1,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T1,T3
1	0	Covered	T18,T19,T20
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1188625967	14043	0	0
GateOpen_A	1188625967	14042	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1188625967	14043	0	0
T1	1919569	105	0	0
T2	360445	0	0	0
T3	2014734	348	0	0
T4	225591	0	0	0
T11	606705	41	0	0
T18	4282	7	0	0
T19	7786	12	0	0
T20	0	15	0	0
T23	7956	4	0	0
T24	45113	0	0	0
T25	13713	0	0	0
T131	0	18	0	0
T132	0	14	0	0
T139	0	16	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1188625967	14042	0	0
T1	1919569	105	0	0
T2	360445	0	0	0
T3	2014734	348	0	0
T4	225591	0	0	0
T11	606705	41	0	0
T18	4282	7	0	0
T19	7786	12	0	0
T20	0	15	0	0
T23	7956	4	0	0
T24	45113	0	0	0
T25	13713	0	0	0
T131	0	18	0	0
T132	0	14	0	0
T139	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T23,T1,T18
0	1	Covered	T23,T1,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T1,T3
1	0	Covered	T18,T19,T20
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	132054625	3423	0	0
GateOpen_A	132054625	3422	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132054625	3423	0	0
T1	210297	26	0	0
T2	40027	0	0	0
T3	221809	86	0	0
T4	16655	0	0	0
T11	67473	10	0	0
T18	469	2	0	0
T19	859	3	0	0
T20	0	4	0	0
T23	867	1	0	0
T24	5494	0	0	0
T25	1515	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T139	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132054625	3422	0	0
T1	210297	26	0	0
T2	40027	0	0	0
T3	221809	86	0	0
T4	16655	0	0	0
T11	67473	10	0	0
T18	469	2	0	0
T19	859	3	0	0
T20	0	4	0	0
T23	867	1	0	0
T24	5494	0	0	0
T25	1515	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T139	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T23,T1,T18
0	1	Covered	T23,T1,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T1,T3
1	0	Covered	T18,T19,T20
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	264110183	3527	0	0
GateOpen_A	264110183	3527	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264110183	3527	0	0
T1	420604	28	0	0
T2	80053	0	0	0
T3	443621	91	0	0
T4	33307	0	0	0
T11	134949	10	0	0
T18	938	2	0	0
T19	1718	3	0	0
T20	0	4	0	0
T23	1733	1	0	0
T24	10992	0	0	0
T25	3030	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T139	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264110183	3527	0	0
T1	420604	28	0	0
T2	80053	0	0	0
T3	443621	91	0	0
T4	33307	0	0	0
T11	134949	10	0	0
T18	938	2	0	0
T19	1718	3	0	0
T20	0	4	0	0
T23	1733	1	0	0
T24	10992	0	0	0
T25	3030	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T139	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T23,T1,T18
0	1	Covered	T23,T1,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T1,T3
1	0	Covered	T18,T19,T20
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	524567662	3566	0	0
GateOpen_A	524567662	3566	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524567662	3566	0	0
T1	851418	26	0	0
T2	160241	0	0	0
T3	887618	89	0	0
T4	117084	0	0	0
T11	267598	9	0	0
T18	1928	2	0	0
T19	3502	3	0	0
T20	0	4	0	0
T23	3571	1	0	0
T24	19084	0	0	0
T25	6112	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T139	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524567662	3566	0	0
T1	851418	26	0	0
T2	160241	0	0	0
T3	887618	89	0	0
T4	117084	0	0	0
T11	267598	9	0	0
T18	1928	2	0	0
T19	3502	3	0	0
T20	0	4	0	0
T23	3571	1	0	0
T24	19084	0	0	0
T25	6112	0	0	0
T131	0	4	0	0
T132	0	3	0	0
T139	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T23,T1,T18
0	1	Covered	T23,T1,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T1,T3
1	0	Covered	T18,T19,T20
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	267893497	3527	0	0
GateOpen_A	267893497	3527	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267893497	3527	0	0
T1	437250	25	0	0
T2	80124	0	0	0
T3	461686	82	0	0
T4	58545	0	0	0
T11	136685	12	0	0
T18	947	1	0	0
T19	1707	3	0	0
T20	0	3	0	0
T23	1785	1	0	0
T24	9543	0	0	0
T25	3056	0	0	0
T131	0	6	0	0
T132	0	5	0	0
T139	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267893497	3527	0	0
T1	437250	25	0	0
T2	80124	0	0	0
T3	461686	82	0	0
T4	58545	0	0	0
T11	136685	12	0	0
T18	947	1	0	0
T19	1707	3	0	0
T20	0	3	0	0
T23	1785	1	0	0
T24	9543	0	0	0
T25	3056	0	0	0
T131	0	6	0	0
T132	0	5	0	0
T139	0	4	0	0