Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	577851	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3283567

1

T8

29

T4

175

T9

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	955650	1			T8	36		T4	192		T9	2
values[0x0]	1336990	1			T8	14		T4	86		T9	4
values[0x1]	1568778	1			T8	13		T4	98		T9	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	321678	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3539740

1

T8

38

T4

219

T9

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14364	1			T7	1		T1	157		T20	1
valid_sources[0x01]	15615	1			T4	1		T1	207		T23	1
valid_sources[0x02]	15613	1			T4	2		T29	3		T7	1
valid_sources[0x03]	15191	1			T4	1		T29	2		T1	172
valid_sources[0x04]	15165	1			T4	1		T37	5		T1	191
valid_sources[0x05]	15377	1			T4	3		T30	5		T1	177
valid_sources[0x06]	15383	1			T1	167		T25	2		T2	636
valid_sources[0x07]	14385	1			T1	197		T23	1		T2	694
valid_sources[0x08]	14354	1			T1	182		T2	628		T12	435
valid_sources[0x09]	13721	1			T4	2		T1	184		T23	3
valid_sources[0x0a]	13977	1			T4	2		T28	1		T1	179
valid_sources[0x0b]	16566	1			T4	1		T29	2		T1	192
valid_sources[0x0c]	13600	1			T4	2		T1	200		T25	1
valid_sources[0x0d]	13394	1			T38	2		T1	184		T25	1
valid_sources[0x0e]	14565	1			T39	1		T1	187		T2	658
valid_sources[0x0f]	15289	1			T4	5		T39	1		T1	203
valid_sources[0x10]	14969	1			T8	1		T4	2		T7	1
valid_sources[0x11]	14161	1			T8	1		T4	2		T7	1
valid_sources[0x12]	14492	1			T8	1		T1	173		T2	641
valid_sources[0x13]	15294	1			T4	1		T9	2		T34	1
valid_sources[0x14]	13497	1			T4	1		T9	1		T7	1
valid_sources[0x15]	15161	1			T4	1		T30	3		T1	198
valid_sources[0x16]	14469	1			T4	2		T1	187		T23	1
valid_sources[0x17]	14759	1			T4	2		T1	164		T2	664
valid_sources[0x18]	15031	1			T1	209		T20	1		T2	715
valid_sources[0x19]	15189	1			T38	2		T1	213		T20	1
valid_sources[0x1a]	15385	1			T8	1		T4	1		T29	1
valid_sources[0x1b]	15234	1			T8	1		T28	1		T29	2
valid_sources[0x1c]	14317	1			T1	198		T21	1		T2	628
valid_sources[0x1d]	15703	1			T29	1		T1	177		T20	1
valid_sources[0x1e]	12955	1			T4	6		T1	199		T25	1
valid_sources[0x1f]	14761	1			T4	4		T39	1		T1	173
valid_sources[0x20]	15021	1			T4	4		T39	1		T1	178
valid_sources[0x21]	14318	1			T8	1		T4	2		T7	2
valid_sources[0x22]	17058	1			T29	1		T1	202		T2	678
valid_sources[0x23]	15356	1			T4	4		T34	4		T37	3
valid_sources[0x24]	15931	1			T4	3		T1	190		T25	3
valid_sources[0x25]	15115	1			T8	2		T4	2		T37	6
valid_sources[0x26]	14646	1			T7	1		T1	193		T23	1
valid_sources[0x27]	14640	1			T4	1		T34	1		T1	195
valid_sources[0x28]	14448	1			T7	2		T1	180		T2	658
valid_sources[0x29]	15126	1			T8	1		T4	1		T30	2
valid_sources[0x2a]	14312	1			T4	3		T7	1		T1	165
valid_sources[0x2b]	13855	1			T8	1		T4	4		T1	186
valid_sources[0x2c]	14057	1			T8	1		T4	3		T1	194
valid_sources[0x2d]	15554	1			T4	1		T29	1		T39	1
valid_sources[0x2e]	14756	1			T4	1		T1	212		T23	2
valid_sources[0x2f]	17815	1			T4	3		T1	168		T20	1
valid_sources[0x30]	15269	1			T4	1		T1	174		T2	686
valid_sources[0x31]	16096	1			T4	1		T7	1		T1	207
valid_sources[0x32]	15248	1			T8	1		T1	186		T2	621
valid_sources[0x33]	14621	1			T1	183		T23	1		T2	648
valid_sources[0x34]	15401	1			T4	5		T34	4		T1	179
valid_sources[0x35]	15847	1			T4	2		T1	186		T2	642
valid_sources[0x36]	15342	1			T8	2		T38	1		T39	1
valid_sources[0x37]	15963	1			T7	1		T40	1		T1	165
valid_sources[0x38]	15038	1			T4	2		T1	175		T20	1
valid_sources[0x39]	17470	1			T4	1		T1	203		T25	1
valid_sources[0x3a]	16242	1			T8	2		T4	1		T7	1
valid_sources[0x3b]	15027	1			T4	2		T39	1		T1	197
valid_sources[0x3c]	14929	1			T8	1		T4	2		T37	13
valid_sources[0x3d]	15192	1			T8	1		T4	1		T9	1
valid_sources[0x3e]	16316	1			T4	2		T29	2		T1	197
valid_sources[0x3f]	14364	1			T8	1		T4	1		T1	189
valid_sources[0x40]	16237	1			T4	3		T1	202		T20	1
valid_sources[0x41]	15202	1			T4	3		T1	189		T2	641
valid_sources[0x42]	15452	1			T4	2		T1	210		T25	3
valid_sources[0x43]	15995	1			T4	2		T30	7		T1	197
valid_sources[0x44]	15696	1			T4	1		T1	162		T20	1
valid_sources[0x45]	16224	1			T4	1		T1	194		T23	2
valid_sources[0x46]	13415	1			T4	1		T39	1		T1	202
valid_sources[0x47]	15819	1			T4	1		T37	1		T1	197
valid_sources[0x48]	14090	1			T8	1		T4	3		T7	1
valid_sources[0x49]	14191	1			T1	176		T20	1		T25	2
valid_sources[0x4a]	14457	1			T8	1		T4	1		T7	2
valid_sources[0x4b]	17047	1			T4	3		T29	2		T1	171
valid_sources[0x4c]	13284	1			T4	2		T7	1		T39	1
valid_sources[0x4d]	13972	1			T4	1		T1	197		T23	1
valid_sources[0x4e]	14838	1			T8	1		T4	2		T37	3
valid_sources[0x4f]	15741	1			T7	1		T37	13		T1	203
valid_sources[0x50]	15054	1			T4	1		T1	181		T20	1
valid_sources[0x51]	15419	1			T1	175		T25	1		T2	626
valid_sources[0x52]	14915	1			T4	1		T7	1		T1	178
valid_sources[0x53]	14072	1			T8	1		T4	2		T29	1
valid_sources[0x54]	15790	1			T4	1		T1	189		T20	1
valid_sources[0x55]	15381	1			T4	2		T1	224		T23	4
valid_sources[0x56]	14374	1			T4	1		T1	209		T2	625
valid_sources[0x57]	15242	1			T8	1		T4	1		T1	173
valid_sources[0x58]	14847	1			T4	4		T1	184		T20	1
valid_sources[0x59]	14933	1			T8	1		T1	181		T25	2
valid_sources[0x5a]	14270	1			T4	1		T7	1		T1	194
valid_sources[0x5b]	15405	1			T37	5		T1	194		T20	1
valid_sources[0x5c]	15267	1			T4	2		T39	1		T1	159
valid_sources[0x5d]	16046	1			T4	2		T38	4		T1	180
valid_sources[0x5e]	16536	1			T8	1		T7	1		T37	1
valid_sources[0x5f]	16114	1			T4	2		T1	182		T2	672
valid_sources[0x60]	14173	1			T4	1		T1	193		T20	1
valid_sources[0x61]	15577	1			T29	1		T37	2		T1	177
valid_sources[0x62]	15414	1			T4	3		T7	2		T37	1
valid_sources[0x63]	14864	1			T4	1		T1	190		T2	636
valid_sources[0x64]	16735	1			T4	2		T7	2		T34	2
valid_sources[0x65]	13796	1			T4	1		T29	1		T1	210
valid_sources[0x66]	15354	1			T7	1		T1	204		T2	658
valid_sources[0x67]	14316	1			T1	199		T2	673		T108	1
valid_sources[0x68]	14766	1			T8	1		T4	1		T1	196
valid_sources[0x69]	15385	1			T4	1		T6	705		T1	198
valid_sources[0x6a]	17961	1			T4	2		T1	186		T23	1
valid_sources[0x6b]	14425	1			T4	2		T1	186		T20	3
valid_sources[0x6c]	14565	1			T4	2		T1	177		T2	642
valid_sources[0x6d]	15595	1			T4	1		T28	1		T7	2
valid_sources[0x6e]	15083	1			T4	3		T7	1		T1	176
valid_sources[0x6f]	14177	1			T4	1		T7	1		T1	190
valid_sources[0x70]	15172	1			T4	1		T29	2		T30	2
valid_sources[0x71]	15420	1			T4	3		T34	1		T1	180
valid_sources[0x72]	16526	1			T4	1		T1	201		T23	1
valid_sources[0x73]	15063	1			T4	2		T34	1		T40	1
valid_sources[0x74]	14797	1			T4	1		T1	183		T20	1
valid_sources[0x75]	14904	1			T8	1		T7	2		T1	189
valid_sources[0x76]	14213	1			T4	3		T37	5		T1	209
valid_sources[0x77]	14838	1			T4	2		T28	5		T7	2
valid_sources[0x78]	15524	1			T4	1		T1	192		T23	1
valid_sources[0x79]	14282	1			T8	1		T4	4		T34	1
valid_sources[0x7a]	13985	1			T4	1		T1	201		T20	1
valid_sources[0x7b]	15616	1			T4	3		T1	164		T23	1
valid_sources[0x7c]	13679	1			T29	1		T1	167		T2	611
valid_sources[0x7d]	14403	1			T4	3		T37	9		T1	187
valid_sources[0x7e]	16704	1			T4	1		T7	1		T37	3
valid_sources[0x7f]	15800	1			T4	2		T1	187		T25	1
valid_sources[0x80]	14146	1			T4	2		T7	1		T1	181

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

832038

1

T8

19

T4

96

T9

1

values[0x0]

all_enables

biggest_size

1248533

1

T8

8

T4

51

T9

1

values[0x1]

all_enables

biggest_size

1202996

1

T8

2

T4

28

T9

1