Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	746892535	72069	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746892535	72069	0	0
T1	903280	921	0	0
T2	0	2464	0	0
T3	0	195	0	0
T12	0	1912	0	0
T13	0	298	0	0
T14	0	254	0	0
T15	0	2834	0	0
T16	0	280	0	0
T17	0	618	0	0
T18	0	52	0	0
T19	11075	0	0	0
T20	11115	0	0	0
T21	4505	0	0	0
T22	6525	0	0	0
T23	15410	0	0	0
T24	5805	0	0	0
T25	505405	0	0	0
T26	16760	0	0	0
T27	5270	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	149378507	10581	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	10581	0	0
T1	180656	122	0	0
T2	0	321	0	0
T3	0	26	0	0
T12	0	269	0	0
T13	0	43	0	0
T14	0	37	0	0
T15	0	419	0	0
T16	0	37	0	0
T17	0	95	0	0
T18	0	9	0	0
T19	2215	0	0	0
T20	2223	0	0	0
T21	901	0	0	0
T22	1305	0	0	0
T23	3082	0	0	0
T24	1161	0	0	0
T25	101081	0	0	0
T26	3352	0	0	0
T27	1054	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	149378507	14432	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	14432	0	0
T1	180656	185	0	0
T2	0	489	0	0
T3	0	40	0	0
T12	0	372	0	0
T13	0	58	0	0
T14	0	51	0	0
T15	0	566	0	0
T16	0	57	0	0
T17	0	123	0	0
T18	0	10	0	0
T19	2215	0	0	0
T20	2223	0	0	0
T21	901	0	0	0
T22	1305	0	0	0
T23	3082	0	0	0
T24	1161	0	0	0
T25	101081	0	0	0
T26	3352	0	0	0
T27	1054	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	149378507	21980	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	21980	0	0
T1	180656	311	0	0
T2	0	809	0	0
T3	0	64	0	0
T12	0	575	0	0
T13	0	88	0	0
T14	0	79	0	0
T15	0	936	0	0
T16	0	94	0	0
T17	0	186	0	0
T18	0	15	0	0
T19	2215	0	0	0
T20	2223	0	0	0
T21	901	0	0	0
T22	1305	0	0	0
T23	3082	0	0	0
T24	1161	0	0	0
T25	101081	0	0	0
T26	3352	0	0	0
T27	1054	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	149378507	10498	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	10498	0	0
T1	180656	119	0	0
T2	0	358	0	0
T3	0	25	0	0
T12	0	266	0	0
T13	0	43	0	0
T14	0	37	0	0
T15	0	356	0	0
T16	0	35	0	0
T17	0	92	0	0
T18	0	8	0	0
T19	2215	0	0	0
T20	2223	0	0	0
T21	901	0	0	0
T22	1305	0	0	0
T23	3082	0	0	0
T24	1161	0	0	0
T25	101081	0	0	0
T26	3352	0	0	0
T27	1054	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	149378507	14578	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	14578	0	0
T1	180656	184	0	0
T2	0	487	0	0
T3	0	40	0	0
T12	0	430	0	0
T13	0	66	0	0
T14	0	50	0	0
T15	0	557	0	0
T16	0	57	0	0
T17	0	122	0	0
T18	0	10	0	0
T19	2215	0	0	0
T20	2223	0	0	0
T21	901	0	0	0
T22	1305	0	0	0
T23	3082	0	0	0
T24	1161	0	0	0
T25	101081	0	0	0
T26	3352	0	0	0
T27	1054	0	0	0