Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T9
0	1	Unreachable
1	0	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	149378507	146547636	0	0
AllClkBypReqTrue_A	149378507	135701	0	0
IoClkBypReqFalse_A	149378507	146460949	0	2415
IoClkBypReqTrue_A	149378507	217724	0	0
LcClkBypAckFalse_A	149378507	146555313	0	0
LcClkBypAckTrue_A	149378507	128024	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	146547636	0	0
T4	15386	3598	0	0
T5	6075	3051	0	0
T7	32153	31912	0	0
T8	1957	1862	0	0
T9	1190	1064	0	0
T28	1819	1594	0	0
T29	2031	1945	0	0
T30	2120	1883	0	0
T31	1835	1633	0	0
T32	1041	927	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	135701	0	0
T1	180656	364	0	0
T2	0	2323	0	0
T6	90393	0	0	0
T19	2215	0	0	0
T20	2223	267	0	0
T22	0	119	0	0
T34	2585	358	0	0
T36	1073	0	0	0
T37	2296	0	0	0
T38	1780	162	0	0
T39	1048	0	0	0
T40	1473	0	0	0
T108	0	52	0	0
T109	0	90	0	0
T110	0	142	0	0
T111	0	14	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	146460949	0	2415
T4	15386	3580	0	3
T5	6075	3039	0	3
T7	32153	31910	0	3
T8	1957	1860	0	3
T9	1190	998	0	3
T28	1819	1592	0	3
T29	2031	1631	0	3
T30	2120	1881	0	3
T31	1835	1631	0	3
T32	1041	925	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	217724	0	0
T1	0	513	0	0
T2	0	4719	0	0
T5	6075	0	0	0
T7	32153	0	0	0
T9	1190	64	0	0
T20	0	424	0	0
T21	0	35	0	0
T22	0	152	0	0
T28	1819	0	0	0
T29	2031	312	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	502	0	0
T36	1073	0	0	0
T38	0	277	0	0
T40	0	43	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	146555313	0	0
T4	15386	3598	0	0
T5	6075	3051	0	0
T7	32153	31912	0	0
T8	1957	1862	0	0
T9	1190	1036	0	0
T28	1819	1594	0	0
T29	2031	1784	0	0
T30	2120	1883	0	0
T31	1835	1633	0	0
T32	1041	927	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	128024	0	0
T1	0	389	0	0
T2	0	3041	0	0
T5	6075	0	0	0
T7	32153	0	0	0
T9	1190	28	0	0
T20	0	275	0	0
T22	0	134	0	0
T28	1819	0	0	0
T29	2031	161	0	0
T30	2120	0	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	184	0	0
T36	1073	0	0	0
T38	0	73	0	0
T40	0	27	0	0
T109	0	112	0	0