Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	149378507	18766911	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149378507	18766911	0	58
T1	180656	204613	0	0
T2	0	125256	0	0
T3	0	23532	0	1
T6	90393	0	0	0
T7	32153	1119	0	1
T12	0	739898	0	0
T13	0	23801	0	1
T14	0	24233	0	0
T15	0	400415	0	0
T16	0	36026	0	1
T18	0	0	0	1
T19	2215	0	0	0
T25	0	1271	0	1
T34	2585	0	0	0
T36	1073	0	0	0
T37	2296	0	0	0
T38	1780	0	0	0
T39	1048	0	0	0
T40	1473	0	0	0
T115	0	0	0	1
T116	0	0	0	1
T117	0	0	0	1
T118	0	0	0	1