Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	150427568	4808437	0	0
clk_enables_rd_A	150427568	43111	0	0
clk_hints_rd_A	150427568	38128	0	0
extclk_ctrl_rd_A	150427568	50341	0	0
extclk_ctrl_regwen_rd_A	150427568	37499	0	0
jitter_enable_rd_A	150427568	56524	0	0
jitter_regwen_rd_A	150427568	42052	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	4808437	0	0
T1	180656	62597	0	0
T2	0	224245	0	0
T12	0	139476	0	0
T15	0	131468	0	0
T17	0	65574	0	0
T19	2215	0	0	0
T20	2223	0	0	0
T21	901	0	0	0
T22	1305	0	0	0
T23	3082	0	0	0
T24	1161	0	0	0
T25	101081	0	0	0
T26	3352	0	0	0
T27	1054	0	0	0
T67	0	70865	0	0
T68	0	63714	0	0
T69	0	48235	0	0
T70	0	174316	0	0
T71	0	13255	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	43111	0	0
T10	89479	0	0	0
T12	490295	5638	0	0
T13	84466	0	0	0
T14	251545	5	0	0
T15	0	5090	0	0
T33	0	5	0	0
T41	1447	0	0	0
T67	0	2610	0	0
T69	0	1773	0	0
T137	2195	3	0	0
T138	0	19	0	0
T139	0	6	0	0
T140	0	2493	0	0
T141	2433	0	0	0
T142	1779	0	0	0
T143	2667	0	0	0
T144	1835	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	38128	0	0
T10	89479	0	0	0
T12	490295	4692	0	0
T13	84466	0	0	0
T14	251545	0	0	0
T15	0	4790	0	0
T41	1447	0	0	0
T67	0	2227	0	0
T69	0	1647	0	0
T116	0	9	0	0
T137	2195	5	0	0
T138	0	15	0	0
T139	0	10	0	0
T140	0	2163	0	0
T141	2433	0	0	0
T142	1779	0	0	0
T143	2667	0	0	0
T144	1835	0	0	0
T145	0	2994	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	50341	0	0
T5	6075	42	0	0
T6	90393	0	0	0
T7	32153	0	0	0
T12	0	5801	0	0
T14	0	117	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	33	0	0
T36	1073	0	0	0
T37	2296	0	0	0
T38	1780	0	0	0
T39	1048	0	0	0
T40	0	4	0	0
T85	0	36	0	0
T86	0	25	0	0
T108	0	18	0	0
T142	0	17	0	0
T144	0	48	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	37499	0	0
T5	6075	14	0	0
T6	90393	0	0	0
T7	32153	0	0	0
T12	0	4714	0	0
T15	0	4533	0	0
T31	1835	0	0	0
T32	1041	0	0	0
T34	2585	0	0	0
T36	1073	0	0	0
T37	2296	0	0	0
T38	1780	0	0	0
T39	1048	0	0	0
T67	0	2151	0	0
T69	0	1424	0	0
T107	0	37	0	0
T140	0	2182	0	0
T146	0	20	0	0
T147	0	43	0	0
T148	0	30	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	56524	0	0
T10	89479	0	0	0
T12	490295	5901	0	0
T13	84466	0	0	0
T14	251545	167	0	0
T15	0	7109	0	0
T33	0	111	0	0
T41	1447	0	0	0
T67	0	3102	0	0
T69	0	2234	0	0
T137	2195	120	0	0
T138	0	432	0	0
T139	0	208	0	0
T140	0	3069	0	0
T141	2433	0	0	0
T142	1779	0	0	0
T143	2667	0	0	0
T144	1835	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150427568	42052	0	0
T10	89479	0	0	0
T12	490295	5524	0	0
T13	84466	0	0	0
T14	251545	0	0	0
T15	0	5298	0	0
T41	1447	0	0	0
T67	0	2806	0	0
T69	0	1736	0	0
T137	2195	0	0	0
T140	0	2654	0	0
T141	2433	0	0	0
T142	1779	0	0	0
T143	2667	0	0	0
T144	1835	0	0	0
T145	0	3155	0	0
T149	0	3441	0	0
T150	0	3554	0	0
T151	0	1867	0	0
T152	0	2740	0	0