Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Covered	T8,T4,T9
1	1	Covered	T8,T4,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	46759	0	0
CgEnOn_A	2147483647	37426	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46759	0	0
T1	0	42	0	0
T4	335123	27	0	0
T5	279149	18	0	0
T6	324274	0	0	0
T7	331549	3	0	0
T8	12541	11	0	0
T9	14908	3	0	0
T27	0	13	0	0
T28	11216	3	0	0
T29	25195	3	0	0
T30	13242	52	0	0
T31	17901	42	0	0
T32	21257	3	0	0
T34	11089	0	0	0
T36	19288	0	0	0
T37	41362	7	0	0
T38	31757	0	0	0
T39	48290	0	0	0
T40	6140	0	0	0
T44	0	15	0	0
T153	0	5	0	0
T154	0	5	0	0
T155	0	20	0	0
T156	0	25	0	0
T157	0	5	0	0
T158	0	15	0	0
T161	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37426	0	0
T1	0	140	0	0
T2	0	545	0	0
T4	227936	0	0	0
T5	279149	0	0	0
T6	488466	0	0	0
T7	331549	0	0	0
T8	8156	8	0	0
T9	9712	0	0	0
T19	0	4	0	0
T24	0	4	0	0
T27	0	19	0	0
T28	7348	0	0	0
T29	16248	0	0	0
T30	13242	49	0	0
T31	17901	39	0	0
T32	21257	0	0	0
T34	16858	0	0	0
T36	29293	16	0	0
T37	62824	7	0	0
T38	48319	0	0	0
T39	48290	0	0	0
T40	6140	0	0	0
T44	0	15	0	0
T112	0	30	0	0
T153	0	5	0	0
T154	0	5	0	0
T155	0	20	0	0
T156	0	25	0	0
T157	0	5	0	0
T158	0	15	0	0
T159	0	2	0	0
T161	0	4	0	0
T162	0	38	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Unreachable
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	195636578	134	0	0
CgEnOn_A	195636578	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195636578	134	0	0
T6	22684	0	0	0
T7	15366	0	0	0
T27	0	2	0	0
T31	781	4	0	0
T32	940	0	0	0
T34	1315	0	0	0
T36	2192	0	0	0
T37	4725	0	0	0
T38	3919	0	0	0
T39	5524	0	0	0
T40	695	0	0	0
T44	0	3	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	3	0	0
T161	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195636578	134	0	0
T6	22684	0	0	0
T7	15366	0	0	0
T27	0	2	0	0
T31	781	4	0	0
T32	940	0	0	0
T34	1315	0	0	0
T36	2192	0	0	0
T37	4725	0	0	0
T38	3919	0	0	0
T39	5524	0	0	0
T40	695	0	0	0
T44	0	3	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	3	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Unreachable
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97817651	134	0	0
CgEnOn_A	97817651	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97817651	134	0	0
T6	11343	0	0	0
T7	7683	0	0	0
T27	0	2	0	0
T31	391	4	0	0
T32	470	0	0	0
T34	656	0	0	0
T36	1096	0	0	0
T37	2362	0	0	0
T38	1959	0	0	0
T39	2762	0	0	0
T40	347	0	0	0
T44	0	3	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	3	0	0
T161	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97817651	134	0	0
T6	11343	0	0	0
T7	7683	0	0	0
T27	0	2	0	0
T31	391	4	0	0
T32	470	0	0	0
T34	656	0	0	0
T36	1096	0	0	0
T37	2362	0	0	0
T38	1959	0	0	0
T39	2762	0	0	0
T40	347	0	0	0
T44	0	3	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	3	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Unreachable
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	393101660	134	0	0
CgEnOn_A	393101660	131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393101660	134	0	0
T6	86775	0	0	0
T7	30867	0	0	0
T27	0	2	0	0
T31	1669	4	0	0
T32	2000	0	0	0
T34	2532	0	0	0
T36	4478	0	0	0
T37	9583	0	0	0
T38	7123	0	0	0
T39	11182	0	0	0
T40	1428	0	0	0
T44	0	3	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	3	0	0
T161	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393101660	131	0	0
T6	86775	0	0	0
T7	30867	0	0	0
T27	0	2	0	0
T31	1669	4	0	0
T32	2000	0	0	0
T34	2532	0	0	0
T36	4478	0	0	0
T37	9583	0	0	0
T38	7123	0	0	0
T39	11182	0	0	0
T40	1428	0	0	0
T44	0	3	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Unreachable
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419349993	123	0	0
CgEnOn_A	419349993	120	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	123	0	0
T6	90393	0	0	0
T7	32153	0	0	0
T27	0	3	0	0
T31	1760	7	0	0
T32	2083	0	0	0
T34	2637	0	0	0
T36	4665	0	0	0
T37	9984	0	0	0
T38	7419	0	0	0
T39	11649	0	0	0
T40	1488	0	0	0
T44	0	1	0	0
T68	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	120	0	0
T6	90393	0	0	0
T7	32153	0	0	0
T27	0	3	0	0
T31	1760	7	0	0
T32	2083	0	0	0
T34	2637	0	0	0
T36	4665	0	0	0
T37	9984	0	0	0
T38	7419	0	0	0
T39	11649	0	0	0
T40	1488	0	0	0
T44	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	2	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Unreachable
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97817651	134	0	0
CgEnOn_A	97817651	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97817651	134	0	0
T6	11343	0	0	0
T7	7683	0	0	0
T27	0	2	0	0
T31	391	4	0	0
T32	470	0	0	0
T34	656	0	0	0
T36	1096	0	0	0
T37	2362	0	0	0
T38	1959	0	0	0
T39	2762	0	0	0
T40	347	0	0	0
T44	0	3	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	3	0	0
T161	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97817651	134	0	0
T6	11343	0	0	0
T7	7683	0	0	0
T27	0	2	0	0
T31	391	4	0	0
T32	470	0	0	0
T34	656	0	0	0
T36	1096	0	0	0
T37	2362	0	0	0
T38	1959	0	0	0
T39	2762	0	0	0
T40	347	0	0	0
T44	0	3	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	3	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Unreachable
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419349993	123	0	0
CgEnOn_A	419349993	120	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	123	0	0
T6	90393	0	0	0
T7	32153	0	0	0
T27	0	3	0	0
T31	1760	7	0	0
T32	2083	0	0	0
T34	2637	0	0	0
T36	4665	0	0	0
T37	9984	0	0	0
T38	7419	0	0	0
T39	11649	0	0	0
T40	1488	0	0	0
T44	0	1	0	0
T68	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	120	0	0
T6	90393	0	0	0
T7	32153	0	0	0
T27	0	3	0	0
T31	1760	7	0	0
T32	2083	0	0	0
T34	2637	0	0	0
T36	4665	0	0	0
T37	9984	0	0	0
T38	7419	0	0	0
T39	11649	0	0	0
T40	1488	0	0	0
T44	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	2	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Unreachable
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97817651	134	0	0
CgEnOn_A	97817651	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97817651	134	0	0
T6	11343	0	0	0
T7	7683	0	0	0
T27	0	2	0	0
T31	391	4	0	0
T32	470	0	0	0
T34	656	0	0	0
T36	1096	0	0	0
T37	2362	0	0	0
T38	1959	0	0	0
T39	2762	0	0	0
T40	347	0	0	0
T44	0	3	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	3	0	0
T161	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97817651	134	0	0
T6	11343	0	0	0
T7	7683	0	0	0
T27	0	2	0	0
T31	391	4	0	0
T32	470	0	0	0
T34	656	0	0	0
T36	1096	0	0	0
T37	2362	0	0	0
T38	1959	0	0	0
T39	2762	0	0	0
T40	347	0	0	0
T44	0	3	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0
T158	0	3	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T27,T44
1	0	Covered	T8,T4,T9
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	195636578	7565	0	0
CgEnOn_A	195636578	5238	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195636578	7565	0	0
T4	16754	9	0	0
T5	16636	6	0	0
T7	15366	1	0	0
T8	966	1	0	0
T9	1134	1	0	0
T28	815	1	0	0
T29	2065	1	0	0
T30	984	17	0	0
T31	781	5	0	0
T32	940	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195636578	5238	0	0
T1	0	33	0	0
T2	0	136	0	0
T5	16636	0	0	0
T6	22684	0	0	0
T7	15366	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T30	984	16	0	0
T31	781	4	0	0
T32	940	0	0	0
T34	1315	0	0	0
T36	2192	6	0	0
T37	4725	0	0	0
T38	3919	0	0	0
T112	0	10	0	0
T162	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T27,T44
1	0	Covered	T8,T4,T9
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	97817651	7503	0	0
CgEnOn_A	97817651	5177	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97817651	7503	0	0
T4	8377	9	0	0
T5	8319	6	0	0
T7	7683	1	0	0
T8	483	1	0	0
T9	567	1	0	0
T28	407	1	0	0
T29	1032	1	0	0
T30	492	19	0	0
T31	391	5	0	0
T32	470	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97817651	5177	0	0
T1	0	31	0	0
T2	0	131	0	0
T5	8319	0	0	0
T6	11343	0	0	0
T7	7683	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T30	492	18	0	0
T31	391	4	0	0
T32	470	0	0	0
T34	656	0	0	0
T36	1096	5	0	0
T37	2362	0	0	0
T38	1959	0	0	0
T112	0	10	0	0
T162	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T27,T44
1	0	Covered	T8,T4,T9
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	393101660	7573	0	0
CgEnOn_A	393101660	5242	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393101660	7573	0	0
T4	54703	9	0	0
T5	44857	6	0	0
T7	30867	1	0	0
T8	1957	1	0	0
T9	2330	1	0	0
T28	1764	1	0	0
T29	3900	1	0	0
T30	2076	16	0	0
T31	1669	5	0	0
T32	2000	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393101660	5242	0	0
T1	0	34	0	0
T2	0	136	0	0
T5	44857	0	0	0
T6	86775	0	0	0
T7	30867	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T30	2076	15	0	0
T31	1669	4	0	0
T32	2000	0	0	0
T34	2532	0	0	0
T36	4478	5	0	0
T37	9583	0	0	0
T38	7123	0	0	0
T112	0	10	0	0
T162	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T27,T44
1	0	Covered	T8,T4,T9
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	201438402	7528	0	0
CgEnOn_A	201438402	5197	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201438402	7528	0	0
T4	27353	9	0	0
T5	22429	6	0	0
T7	15433	1	0	0
T8	979	1	0	0
T9	1165	1	0	0
T28	882	1	0	0
T29	1950	1	0	0
T30	1038	16	0	0
T31	877	6	0	0
T32	999	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201438402	5197	0	0
T1	0	33	0	0
T2	0	137	0	0
T5	22429	0	0	0
T6	43390	0	0	0
T7	15433	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	3	0	0
T30	1038	15	0	0
T31	877	5	0	0
T32	999	0	0	0
T34	1266	0	0	0
T36	2239	5	0	0
T37	4792	0	0	0
T38	3561	0	0	0
T112	0	9	0	0
T162	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Covered	T8,T37,T1
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419349993	3908	0	0
CgEnOn_A	419349993	3907	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	3908	0	0
T1	0	42	0	0
T2	0	142	0	0
T4	56984	0	0	0
T5	46727	0	0	0
T7	32153	0	0	0
T8	2039	8	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	6	0	0
T24	0	1	0	0
T26	0	9	0	0
T27	0	3	0	0
T28	1837	0	0	0
T29	4062	0	0	0
T30	2163	0	0	0
T31	1760	7	0	0
T32	2083	0	0	0
T37	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	3907	0	0
T1	0	42	0	0
T2	0	142	0	0
T4	56984	0	0	0
T5	46727	0	0	0
T7	32153	0	0	0
T8	2039	8	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	6	0	0
T24	0	1	0	0
T26	0	9	0	0
T27	0	3	0	0
T28	1837	0	0	0
T29	4062	0	0	0
T30	2163	0	0	0
T31	1760	7	0	0
T32	2083	0	0	0
T37	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Covered	T8,T32,T37
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419349993	3934	0	0
CgEnOn_A	419349993	3932	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	3934	0	0
T1	0	51	0	0
T4	56984	0	0	0
T5	46727	0	0	0
T7	32153	0	0	0
T8	2039	4	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	4	0	0
T24	0	1	0	0
T26	0	9	0	0
T27	0	3	0	0
T28	1837	0	0	0
T29	4062	0	0	0
T30	2163	0	0	0
T31	1760	7	0	0
T32	2083	1	0	0
T37	0	12	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	3932	0	0
T1	0	51	0	0
T4	56984	0	0	0
T5	46727	0	0	0
T7	32153	0	0	0
T8	2039	4	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	4	0	0
T24	0	1	0	0
T26	0	9	0	0
T27	0	3	0	0
T28	1837	0	0	0
T29	4062	0	0	0
T30	2163	0	0	0
T31	1760	7	0	0
T32	2083	1	0	0
T37	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Covered	T8,T37,T1
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419349993	3878	0	0
CgEnOn_A	419349993	3875	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	3878	0	0
T1	0	38	0	0
T2	0	136	0	0
T4	56984	0	0	0
T5	46727	0	0	0
T7	32153	0	0	0
T8	2039	3	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	7	0	0
T24	0	1	0	0
T26	0	11	0	0
T27	0	3	0	0
T28	1837	0	0	0
T29	4062	0	0	0
T30	2163	0	0	0
T31	1760	7	0	0
T32	2083	0	0	0
T37	0	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	3875	0	0
T1	0	38	0	0
T2	0	136	0	0
T4	56984	0	0	0
T5	46727	0	0	0
T7	32153	0	0	0
T8	2039	3	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	7	0	0
T24	0	1	0	0
T26	0	11	0	0
T27	0	3	0	0
T28	1837	0	0	0
T29	4062	0	0	0
T30	2163	0	0	0
T31	1760	7	0	0
T32	2083	0	0	0
T37	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Covered	T8,T32,T37
1	1	Covered	T8,T4,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419349993	3954	0	0
CgEnOn_A	419349993	3951	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	3954	0	0
T1	0	45	0	0
T4	56984	0	0	0
T5	46727	0	0	0
T7	32153	0	0	0
T8	2039	3	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	8	0	0
T24	0	1	0	0
T26	0	12	0	0
T27	0	3	0	0
T28	1837	0	0	0
T29	4062	0	0	0
T30	2163	0	0	0
T31	1760	7	0	0
T32	2083	1	0	0
T37	0	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419349993	3951	0	0
T1	0	45	0	0
T4	56984	0	0	0
T5	46727	0	0	0
T7	32153	0	0	0
T8	2039	3	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	8	0	0
T24	0	1	0	0
T26	0	12	0	0
T27	0	3	0	0
T28	1837	0	0	0
T29	4062	0	0	0
T30	2163	0	0	0
T31	1760	7	0	0
T32	2083	1	0	0
T37	0	11	0	0