Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T1
0	1	Covered	T30,T36,T1
1	0	Covered	T8,T29,T30

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T36,T1
1	0	Covered	T31,T27,T44
1	1	Covered	T8,T29,T30

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	887995917	13282	0	0
GateOpen_A	887995917	13279	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	887995917	13282	0	0
T1	0	73	0	0
T2	0	377	0	0
T5	92244	0	0	0
T6	164194	0	0	0
T7	69352	0	0	0
T19	0	4	0	0
T24	0	4	0	0
T27	0	9	0	0
T30	4593	53	0	0
T31	3721	17	0	0
T32	4411	0	0	0
T34	5769	0	0	0
T36	10007	0	0	0
T37	21464	0	0	0
T38	16565	0	0	0
T112	0	39	0	0
T113	0	4	0	0
T162	0	35	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	887995917	13279	0	0
T1	0	73	0	0
T2	0	377	0	0
T5	92244	0	0	0
T6	164194	0	0	0
T7	69352	0	0	0
T19	0	4	0	0
T24	0	4	0	0
T27	0	9	0	0
T30	4593	53	0	0
T31	3721	17	0	0
T32	4411	0	0	0
T34	5769	0	0	0
T36	10007	0	0	0
T37	21464	0	0	0
T38	16565	0	0	0
T112	0	39	0	0
T113	0	4	0	0
T162	0	35	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T1
0	1	Covered	T30,T36,T1
1	0	Covered	T8,T29,T30

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T36,T1
1	0	Covered	T31,T27,T44
1	1	Covered	T8,T29,T30

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	97818048	3295	0	0
GateOpen_A	97818048	3294	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97818048	3295	0	0
T1	0	17	0	0
T2	0	91	0	0
T5	8320	0	0	0
T6	11344	0	0	0
T7	7684	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T30	493	14	0	0
T31	391	4	0	0
T32	470	0	0	0
T34	656	0	0	0
T36	1097	0	0	0
T37	2363	0	0	0
T38	1960	0	0	0
T112	0	10	0	0
T113	0	1	0	0
T162	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97818048	3294	0	0
T1	0	17	0	0
T2	0	91	0	0
T5	8320	0	0	0
T6	11344	0	0	0
T7	7684	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T30	493	14	0	0
T31	391	4	0	0
T32	470	0	0	0
T34	656	0	0	0
T36	1097	0	0	0
T37	2363	0	0	0
T38	1960	0	0	0
T112	0	10	0	0
T113	0	1	0	0
T162	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T1
0	1	Covered	T30,T36,T1
1	0	Covered	T8,T29,T30

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T36,T1
1	0	Covered	T31,T27,T44
1	1	Covered	T8,T29,T30

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	195636968	3309	0	0
GateOpen_A	195636968	3308	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195636968	3309	0	0
T1	0	18	0	0
T2	0	96	0	0
T5	16637	0	0	0
T6	22685	0	0	0
T7	15367	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T30	985	13	0	0
T31	782	4	0	0
T32	940	0	0	0
T34	1315	0	0	0
T36	2193	0	0	0
T37	4725	0	0	0
T38	3919	0	0	0
T112	0	10	0	0
T113	0	1	0	0
T162	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195636968	3308	0	0
T1	0	18	0	0
T2	0	96	0	0
T5	16637	0	0	0
T6	22685	0	0	0
T7	15367	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T30	985	13	0	0
T31	782	4	0	0
T32	940	0	0	0
T34	1315	0	0	0
T36	2193	0	0	0
T37	4725	0	0	0
T38	3919	0	0	0
T112	0	10	0	0
T113	0	1	0	0
T162	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T1
0	1	Covered	T30,T36,T1
1	0	Covered	T8,T29,T30

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T36,T1
1	0	Covered	T31,T27,T44
1	1	Covered	T8,T29,T30

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	393102103	3366	0	0
GateOpen_A	393102103	3366	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393102103	3366	0	0
T1	0	20	0	0
T2	0	91	0	0
T5	44857	0	0	0
T6	86775	0	0	0
T7	30867	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T30	2077	14	0	0
T31	1670	4	0	0
T32	2001	0	0	0
T34	2532	0	0	0
T36	4478	0	0	0
T37	9584	0	0	0
T38	7124	0	0	0
T112	0	10	0	0
T113	0	1	0	0
T162	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393102103	3366	0	0
T1	0	20	0	0
T2	0	91	0	0
T5	44857	0	0	0
T6	86775	0	0	0
T7	30867	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T30	2077	14	0	0
T31	1670	4	0	0
T32	2001	0	0	0
T34	2532	0	0	0
T36	4478	0	0	0
T37	9584	0	0	0
T38	7124	0	0	0
T112	0	10	0	0
T113	0	1	0	0
T162	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T1
0	1	Covered	T30,T36,T1
1	0	Covered	T8,T29,T30

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T36,T1
1	0	Covered	T31,T27,T44
1	1	Covered	T8,T29,T30

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	201438798	3312	0	0
GateOpen_A	201438798	3311	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201438798	3312	0	0
T1	0	18	0	0
T2	0	99	0	0
T5	22430	0	0	0
T6	43390	0	0	0
T7	15434	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	3	0	0
T30	1038	12	0	0
T31	878	5	0	0
T32	1000	0	0	0
T34	1266	0	0	0
T36	2239	0	0	0
T37	4792	0	0	0
T38	3562	0	0	0
T112	0	9	0	0
T113	0	1	0	0
T162	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201438798	3311	0	0
T1	0	18	0	0
T2	0	99	0	0
T5	22430	0	0	0
T6	43390	0	0	0
T7	15434	0	0	0
T19	0	1	0	0
T24	0	1	0	0
T27	0	3	0	0
T30	1038	12	0	0
T31	878	5	0	0
T32	1000	0	0	0
T34	1266	0	0	0
T36	2239	0	0	0
T37	4792	0	0	0
T38	3562	0	0	0
T112	0	9	0	0
T113	0	1	0	0
T162	0	9	0	0